I am trying to simulate a low voltage ride through (LVRT) lagging case (Qgenerator = max). The inverter seems to be going to momentary cessation, and although the output power at the inverter terminals is 0, the power at the infinite bus is not 0. Is this something related to the PSSE simulator, or is there some theory that I am missing?
I will attach screenshots of the plots as reference, and in case you need anything else please let me know. Any help is appreciated.