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Reprogrammability in FPGAs comes from 2 building blocks: configurable logic blocks (LUTs) and switching matrix.

It is often said that the HDL code gets translated into the corresponding LUT logic, but what happens to the programmable interconnects?

How does any HDL code interact with switching matrix in FPGA?

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well, of course the HDL code gets converted into connected logic, not only logic: What good would unconnected LUTs do? They'd not be representing the HDL functionality.

So, yeah. That routing is part of the synthesis/Place-and-Route, just like the mapping to LUTs. One without the other makes no sense!

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  • \$\begingroup\$ Could you please share what part of the HDL code refers to that connected logic? \$\endgroup\$
    – lousycoder
    Jul 26, 2022 at 11:27
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    \$\begingroup\$ all of it. the wiring between the LUTs is just as much part of the logic as the LUTs. \$\endgroup\$ Jul 26, 2022 at 12:19
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    \$\begingroup\$ @lousycoder which part of the assembly code refers to the clock cycles? \$\endgroup\$
    – user253751
    Aug 3, 2022 at 20:05
  • \$\begingroup\$ Clock cycles details are abstracted away from the assembly language view. \$\endgroup\$
    – lousycoder
    Aug 12, 2022 at 16:04
  • \$\begingroup\$ @lousycoder no, they are completely undefined by the assembler. The comparison is not a good one. \$\endgroup\$ Aug 15, 2022 at 10:24
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Many of the connections (wires) are what get put in the "switching matrix" also called "routing resources".

The synthesis step of Verilog (or VHDL) compilation converts your code into a set of primitive logic functions (flip-flops, muxes, AND gates, etc) and interconnect. It can be informative to inspect the schematic generated by the compiler.

The MAP step maps these logic functions into the programmable structures of the targeted device. The interconnect is, of course, retained.

Finally, the FIT step places these logic functions in the targeted device ensuring that all interconnect can be completed (and usually checking timing as well). There is quite a bit to all this, with things like dedicated clock trees, and IO structure instantiation. In the early days of FPGA using HDL, one had to explicitly add IO using structural verilog (or schematics!).

So, the fitter (part of the FPGA vendors toolchain) is the thing that decides what goes where, and how best to use routing resources (buffers and wires) to connect all the logic elements together.

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