Many of the connections (wires) are what get put in the "switching matrix" also called "routing resources".
The synthesis step of Verilog (or VHDL) compilation converts your code into a set of primitive logic functions (flip-flops, muxes, AND gates, etc) and interconnect. It can be informative to inspect the schematic generated by the compiler.
The MAP step maps these logic functions into the programmable structures of the targeted device. The interconnect is, of course, retained.
Finally, the FIT step places these logic functions in the targeted device ensuring that all interconnect can be completed (and usually checking timing as well). There is quite a bit to all this, with things like dedicated clock trees, and IO structure instantiation. In the early days of FPGA using HDL, one had to explicitly add IO using structural verilog (or schematics!).
So, the fitter (part of the FPGA vendors toolchain) is the thing that decides what goes where, and how best to use routing resources (buffers and wires) to connect all the logic elements together.