I have a 555 timer circuit that looks like this:


simulate this circuit – Schematic created using CircuitLab

(Trigger I believe should be active low, but the circuit tool doesn't show that in the standard part)

I need to add a delay to this circuit such that any signal coming through the optocoupler less than 100ms in length does not cause the 555 to trigger. The timing isn't critical +/- 10%. I had thought to add an RC delay here but because this is active-low I'm not sure if an RC is appropriate. I believe that this can be done with an appropriate sized capacitor between TRIGGER and +5V to hold up the trigger line when Q1 goes low, but I'm not sure how to size that capacitor.

I also realize that this could be done by cascading 555's but I'd like to avoid that if possible.

The solution that I came up with is to add a .22uF capacitor on the trigger line to ground, is this an acceptable way to hold up the trigger for 100ms?

  • \$\begingroup\$ Problem is, if a 50ms trigger pulse arrives, it will partially charge the input capacitor so that if another short (say) 70ms trigger pulse arrives shortly after the first 50ms pulse then the capacitor will be charged enough already to trigger the 555. So is it acceptable to assume that the time between short trigger pulses arriving is long enough to give the added capacitor time to completely discharge? What is the minimum time between trigger pulses arriving? \$\endgroup\$
    – user173271
    Jul 26, 2022 at 23:27
  • \$\begingroup\$ The trigger to the opto is a rare event, there may be some bounce as things are connected (once at set up then may sit for years), but a "real" event doesn't happen but once every few days at the most. \$\endgroup\$
    – OleSparky
    Jul 26, 2022 at 23:50

1 Answer 1


You are right, the 555 trigger is active low, the trigger pin must be taken below Vcc/3 to trigger the 555 or in your case approx 5/3 = 1.666 V

When Q1 switches on, its collector goes to approx 0 V instantly putting about 5V across R2 and C1 starts to charge. If the input pulse is long enough, the bottom of C1 will eventually reach about 0.45 V, reaching 1.666 V to trigger the 555 after about 100 ms.

If the input pulse is shorter than 100ms then the bottom of C1 will not reach down to 1.666 V and the 555 won't trigger.



After the 555 has been triggered you must ensure that pin 2 (Trigger pin) gets back up above 1.66 V before the end of the 555's output pulse or the output pulse will be extended until pin 2 does rise above 1.66 V.

  • \$\begingroup\$ Can you elaborate on how you came to the values for R1, R2. and C1? \$\endgroup\$
    – OleSparky
    Jul 27, 2022 at 1:33
  • \$\begingroup\$ @OleSparky A ratio for R1:R2 of 10:1 means that, for a lengthy input pulse, the bottom of C1 will come to rest at about 0.45 V which is lower than the 1.66 V trigger threshold thus ensuring triggering. Then it's a matter of considering the Thevenin equiv circuit which is a 0.45 V voltage source charging the capacitor through a single resistor (Thevenin resistance) of value R1//R2 and using the equation t = T.ln(Vo/V) where t= 100ms, Vo is the initial voltage across the thevenin resistance (5 - 0.45) and V is the voltage across the Thevenin resistance at the switching threshold ..... \$\endgroup\$
    – user173271
    Jul 27, 2022 at 6:26
  • \$\begingroup\$ .... (1.66 - .45). The value for T is equal to the RC time constant. (R1//R2).C and first I tried values for R1 & R2 of 100k and 10k with C = 10uF but t came out a little higher than 100ms so I tried lower values of 82k and 8k2 and t came out just about 100ms. So, with those values, 100ms is the time it takes for the bottom of C to charge down to the switching threshold (1.66 V). \$\endgroup\$
    – user173271
    Jul 27, 2022 at 6:32

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