I am putting an Infineon TLE8386 boost controller on a board. It uses an external FET, I have selected one in a TO263 (D2PAK) and I am trying to work out the compromise between heat-sinking and ground plane integrity.
The relevant part of the schematic is show here
The FET has the heatsink connected to pin 2, net
SWITCH_HI. As you can see, this means I cannot use the ground plane as a heatsink. Intuitively, a FET that has the heatsink connected to source may be better for a boost topology, but in this application the source does not connect directly to ground either, instead going through a current sense resistor (R36).
Considering the current on these nets: We have switching edges occurring at both the drain and source of the FET, both nodes of the diode and both nodes of the current sense resistor. Considering the voltages,
SWITCH_HI will be transitioning approximately between input voltage and output voltage, that could be up to 12V p-p. Voltage on
SWCS will be much smaller transitions and closer to ground.
So with reference to an Application Note on TO263 heat-sinking I have come up with the following layout
For clarity I've made the inner layers invisible.
SWITCH_HI is highlighted. I have connected it to all 4 layers with 0.3mm drill vias in the pads, and 0.4mm drill vias elsewhere. It is surrounded by
GND ON 3 sides. The bottom side meets up with the ground plane on two layers and on the other two layers there is another pour
AUX_V+ which is the cathode of the diode and the output of the boost converter (this is the pour you can see beneath the text
The diode can be seen towards the left of the
SWITCH_HI on the underside (blue).
I have taken the routing-on-inner-layers approach, though on most of the board the routing is quite sparse and the inner copper ground pours are as good as the designated ground planes top and bottom. There are however components both top and bottom side in close vicinity of the
As you can see, this makes a squarish hole in my ground plane, on all layers.
So I was wondering, what are the consequences (EMC or otherwise) of making a big hole in my ground plane, and filling it with a high-current switching signal? And what should I do to mitigate it?
Options could include fencing, or restricting the
SWITCH_HI pour to just the inner layers. I'm not sure how that would affect heat dissipation, and in any case there are some sufficiently large pads on
SWITCH_HI that by necessity of them being part of a component must be on the outer layers.
Layout was always someone else's job, and I really have no idea how good or bad this is as it currently stands.