I am putting an Infineon TLE8386 boost controller on a board. It uses an external FET, I have selected one in a TO263 (D2PAK) and I am trying to work out the compromise between heat-sinking and ground plane integrity.

The relevant part of the schematic is show here boost converter schematic exceprt

The FET has the heatsink connected to pin 2, net SWITCH_HI. As you can see, this means I cannot use the ground plane as a heatsink. Intuitively, a FET that has the heatsink connected to source may be better for a boost topology, but in this application the source does not connect directly to ground either, instead going through a current sense resistor (R36).

Considering the current on these nets: We have switching edges occurring at both the drain and source of the FET, both nodes of the diode and both nodes of the current sense resistor. Considering the voltages, SWITCH_HI will be transitioning approximately between input voltage and output voltage, that could be up to 12V p-p. Voltage on SWCS will be much smaller transitions and closer to ground.

So with reference to an Application Note on TO263 heat-sinking I have come up with the following layout Boost Layout

For clarity I've made the inner layers invisible.

The net SWITCH_HI is highlighted. I have connected it to all 4 layers with 0.3mm drill vias in the pads, and 0.4mm drill vias elsewhere. It is surrounded by GND ON 3 sides. The bottom side meets up with the ground plane on two layers and on the other two layers there is another pour AUX_V+ which is the cathode of the diode and the output of the boost converter (this is the pour you can see beneath the text AUX-OUT).

The diode can be seen towards the left of the SWITCH_HI on the underside (blue).

I have taken the routing-on-inner-layers approach, though on most of the board the routing is quite sparse and the inner copper ground pours are as good as the designated ground planes top and bottom. There are however components both top and bottom side in close vicinity of the SWITCH_HI pour.

As you can see, this makes a squarish hole in my ground plane, on all layers.

So I was wondering, what are the consequences (EMC or otherwise) of making a big hole in my ground plane, and filling it with a high-current switching signal? And what should I do to mitigate it?

Options could include fencing, or restricting the SWITCH_HI pour to just the inner layers. I'm not sure how that would affect heat dissipation, and in any case there are some sufficiently large pads on SWITCH_HI that by necessity of them being part of a component must be on the outer layers.

Layout was always someone else's job, and I really have no idea how good or bad this is as it currently stands.

  • \$\begingroup\$ Sorry, but I can't work out from your PCB image just where the transistor attaches and where the current flows from the transistor pin 2 to the coil and diode. That would change how the current might flow through all those vias. For example, is the trace carrying that current on the same side as the pin 2 attachment? And how many of those vias are underneath the pin 2 tab when it is soldered down? \$\endgroup\$
    – emrys57
    Commented Jul 27, 2022 at 13:45
  • \$\begingroup\$ The reddish areas are top side pads, the larger one to the right is of the highlighted net is pin 2 of the FET. The pad nearer the middle is from the inductor. The diode is on the other side, the blueish pad on the middle left is the anode, the cathode (on a different net) is the lower left pad which cuts the corner of the pour. Please let me know if you think the colours are a problem for some people or some devices. \$\endgroup\$
    – Rodney
    Commented Jul 27, 2022 at 13:53
  • \$\begingroup\$ Also the current enters the net from the inductor and leaves via the transistor (when it is switched on) or via the diode (when the transistor is off) \$\endgroup\$
    – Rodney
    Commented Jul 27, 2022 at 13:56
  • \$\begingroup\$ So what's that trace going north from the middle of the FET pin 2 pad? And how big is the peak current? Actually, personally, I'm guessing you won't have any problems at all here, but I'd like to be able to offer a quantitative answer. \$\endgroup\$
    – emrys57
    Commented Jul 27, 2022 at 14:07
  • \$\begingroup\$ So pin 2 is in the footprint "twice", as the middle pin and as the heatsink tab. KiCad drew a ratsnest wire between the two so I just joined it. It's a good point, I should check whether that actual package even has that middle pin and modify the footprint if not. Peak current is 6A ish. \$\endgroup\$
    – Rodney
    Commented Jul 27, 2022 at 14:11

3 Answers 3


You have two major ground loops for your switching currents, and you want to make them as tight as possible, without disruptions of the underlying ground plane.

Both loops start out with your input cap (not shown, but I'm hoping it's there). The current passes through the cap from ground, and then through the inductor.

The first one then passes through the transistor and sense resistor back to ground.

The second one passes through the diode and output cap to ground.

In both cases, of course, the ground path back to the input cap is also part of the loop. Both loops should be as tight as possible and enjoy continuous ground plane beneath them. As much as possible, keeping the tracks on the top layer is preferred.

If you want to post your layout with both loops marked out, I'll offer my opinion,

  • \$\begingroup\$ The input capacitor is on the bottom left of the picture, you can just see half of it. The loops you mention look good apart from the path from the current sense resistor down to the capacitors is a bit obstructed - I'll try and sort that out and put and updated picture. \$\endgroup\$
    – Rodney
    Commented Jul 28, 2022 at 10:55
  • \$\begingroup\$ @Rodney I have to ask, what the point is of burying that patch of SWITCH_HI rather than just flooding the top of the board? It seems you could get the same area or more, with the extra benefit of convection cooling on the external layers. You'd still have the same four vias connecting the drain pad to the flood. (Also, the reason the drain is used as a heat sink is due usually to the transistor construction itself; the bulk of the die is electrically drain, including the bottom.) \$\endgroup\$ Commented Jul 28, 2022 at 14:28
  • \$\begingroup\$ It's not buried it's on all four layers. I think it just looks that way in the CAD tool. The pads and tracks are solid but the pours are translucent, resulting in weird shades when you have a pour on more than one layer. \$\endgroup\$
    – Rodney
    Commented Jul 29, 2022 at 23:29

Simple: don't cut the inner layers!

In fact, you'll get better heat dissipation (more lateral spreading) with the layers in place.

Make dense rows/blocks of vias, near the large pad (can be inside if via-in-pad is acceptable for your soldering process), while leaving adequate space between blocks for inner layers to flow.

You can also set top-middle-bottom padstack for the vias, and reduce or remove inner annulus (it will be removed anyway during fab generation, if those rings are unconnected), to get tighter clearance between inner copper and the hole. Sometimes this is worthwhile to increase the inner layer cross-section, or indeed get connectivity at all. Mind to set relatively wide clearances, as the tolerance from final drilling to inner copper is looser than usual (I would recommend ≥ 0.25mm from hole edge to isolated inner copper).

Regarding the appnote: I mean, in general, read them with skepticism. They are rarely authoritative, and often just not good. This one, looks fine for what it is -- it's well enough written, and contains lots of reasonable looking data. But keep in mind what they do not cover:

  • They are not using wide inner planes
  • They do not test other via patterns, or attempt to optimize them
  • They make no attempt to explain their findings (e.g. why is soldermask worse: is the thermal conductivity or radiative emissivity dominant?)
  • They do not test for solder-filled vias (probably relevant for wave soldering process)
  • They do not test at higher temperatures/rises, or with forced air of given velocity

So, it's good as a comparison between the options presented, but what they present is far from an exhaustive list, and there's only measurements under the given conditions, and there's no analysis.

FYI, about that one: if your vias happen to fill with solder, expect roughly twice the thermal conductivity. Solder is a relatively poor conductor, but because there's so much less copper in the "barrel" and so much more solder, it's a meaningful difference! Downsides include: thieving solder from the pad, if applicable (always a concern with via-in-pad design); and an uneven surface for further heatsinking: the solder may diple into the via hole, or bulge out from it; a flexible (soft or "ultra soft") thermal pad may be required, instead of a thinner insulator, or direct greased joint if applicable.


Making large holes on a ground (or any other power) plane is generally not a good thing because this creates alternate paths for (return) currents i.e. loops.

Considering the voltages, SWITCH_HI will be transitioning approximately between input voltage and output voltage,

No. The switch voltage will be pulsating between 0V and output voltage (neglecting diode drop). Inductor voltage will be pulsating between input voltage and "minus" output-input difference which equals to Vo-pp.

In terms of EMC, you should worry more about the high dv/dt and high di/dt lines. As these lines get longer, due to the high frequency content of these switching lines, conducted and radiated emissions may get worse (not only because of this, but this still plays an important role) due to the antenna effect of the tracks. And also it's worth to remind that CCM is better than DCM. So, by design, you should guarantee CCM operation when the converter is loaded.

  • \$\begingroup\$ I am going to review the answers in more detail tomorrow but for now just wanted to say you are correct about SWITCH_HI voltage going to near ground when the FET is conducting, my mistake. \$\endgroup\$
    – Rodney
    Commented Jul 27, 2022 at 21:58

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