# Derivation help: gain of 2 NMOS in series

I am trying to find the gain (Vout/Vin) of the circuit below, this is not a real circuit that I have, I am just trying to learn more about circuit analysis. The circuit reminds me of a cascode circuit where the gates are the same potential instead of one being Common Gate.

How/where do I start to derive this?

Why is M1 in triode region?

Why is M2 in saturation region?

I did a small signal model analysis followed by short circuiting the output to ground. I followed this up with inserting a test voltage and setting vin to 0V.

Out of this, I got a gain of gm1*(ro1+ro2) . However I am not sure if this is correct. Any help is appreciated

• I think the gain question should be a separate question from the sat/triode question. I've answered the second below.
– pat
Commented Aug 1, 2022 at 20:22

As stated in my previous answer, I thought that the intrinsic gain was $$\ G_{eq} = g_{m}*(r_{o1}+r_{o2}) \$$.

So I tried simulating both the circuit in question with 2 identical N-mosfets and a normal N-mosfet common source amplifier. for my simulations I've used the Microcap spice simulator with the 2N7002 model for the mosfets.

First, the CS Amplifier :

I've chosen to run the simulations at the operating point : $$\V_{gs}=3.5V , I_{D}=100mA\$$ (Dont mind the "AC 0.1", the plots were adjusted accordingly)

For your circuit, I thought that I would see a $$\+6dB\$$ increase. However the gain doubled (well, in decibels..):

The gain got squared ! It went from $$\ 49.3 dB \$$ to $$\ 98.6 dB \$$. This looks exactly like a cascode amplifier but with the $$\ 180° \$$ phase shift of a CS amplifier.

For a sanity check, I've simulated the equivalent cascode amplifier :

The intrinsic gain isn't the same since the operating point definition is different for each amplifier. But overall the two amplifiers behave similarly in term of gain.

## Back to the drawing board

Let's try to find the Gain and Output impedance of your Amplifier with two different mosfets.

#### Gain :

The hybrid Pi-model for low frequencies is the following (By Krishnavedala - Own work, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=36311653):

The amplifier then becomes (Drawn by me):

The output voltage can be written as (Implying an Ideal current source):

$$$$V_{out} = V_{DS2} + V_{S2}$$$$

with :

$$$$V_{DS2} = -g_{m2}r_{o2}(V_{in}-V_{S2})$$$$

and

$$$$V_{S2} = -g_{m1}r_{o1}V_{in}$$$$

After substitution :

$$$$V_{out} = -[g_{m1}g_{m2}r_{o1}r_{o2}+g_{m1}r_{o1}+g_{m2}r_{o2}-1]V_{in}$$$$

So, the intrinsic Gain can be approximated to :

$$$$G = -g_{m1}g_{m2}r_{o1}r_{o2}$$$$

This approximation works since the gain $$\ g_{m}r_{o} \$$ is always higher than 20.

At this stage, we can see that $$\ V_{S2} \$$ is always $$\ g_{m2}r_{o2} \$$ times lower than $$\ V_{out} \$$. This might explain why M1 is in triode region.

#### Output Impedance : #### (In progress)

• If the source impedance is zero, the FET gate capacitance is neutralized, so you do get over the top gain. Commented Jul 31, 2022 at 21:38
• Can you really say that Vds2 = -gm2*ro2*(Cin-Vs2) ? The current across Ro2 will not solely be from the top current source. Commented Aug 1, 2022 at 3:17
• @bobflux can you elaborate on why does that happens, please ? Commented Aug 1, 2022 at 8:12
• @Jirhska No, i don't think there is another current that can flow through Ro2. The bottom current source can't provide current to Ro2 since there is no path back to the source. And the Ideal current source (Ir in your schematics) is replaced by an open (since it's a dc value and this is a small signal analysis) and its resistance of infinity to ground. Commented Aug 1, 2022 at 8:18
• The MOSFET has gate capacitance. When driven by an AC voltage, it will draw current. Combined with the output impedance of whatever is driving it, this sets a limit to bandwidth. Using a voltage source with zero resistance to drive it will result in unrealistic high bandwidth. Commented Aug 1, 2022 at 9:26

Why is M1 in triode region? Why is M2 in saturation region?

Start by assuming same W/L ratio for both devices. Then, if you imagine that both devices have a specific Id vs Vds curve for one specific Vgs and Ir, then each has one specific Vgs that will give Ir for the specific W/L and Vgs.

If this is true (which it is), then you can see that if vin = Vgs1 the voltage at the gate only has enough voltage to supply one full Vgs to both devices, but the M2 would have 0 volt left to supply M1 vds > 0. And M1 vds needs to be a minimum value to be saturated. So right away, M1 cannot be saturated.

M1 has a fixed Id vs Vds curve for a fixed Vgs, but M2 can adjust it's Vs, or equivalently, shift its specific Vgs curve, to get both devices to some operating point to have the same Id (via loop feedback in the circuit configuration).

Now, M1 will move backwards on it's fixed (Vgs) Id vs Vds curve until both currents equalize to a lower value and M1 moves all the way to triode, the top device M2, will adjust by shifting its Vgs (by adjusting the s value and hence Vd to M1) to give equivalent Id as this new M1 operating point in triode. So top device M2 is now is still in saturation (but on a shifted Id/Vds Vgs operating curve), and M1 is the original Id/Vds Vgs curve but operating way back in triode. You'll also notice the original expected current is no longer the same, because the current had to drop for the devices to equalize to the same current.

>How/where do I start to derive this?

I don't know how to derive $$\ G_{eq} = g_{m}*(r_{o1}+r_{o2}) \$$ from two random transistors with different characteristics.

However, if I suppose that the 2 mosfets are planar and have the same $$\ W\$$ and $$\ L\$$ (channel width and length), we can think of them as stacked-up mosfets :

(Image drawn by me)

The equivalent mosfet would have a channel length of $$\ 2L\$$ (approx.) and a width of $$\ W\$$.

The output resistance formula is :

$$\ r_{o,eq} \approx \frac{1}{\lambda I_D}\$$

with $$\ \lambda \approx {\frac {\Delta L}{V_{E}L_{eq}}} \$$

Since we have doubled the channel Length, then $$\ r_{o,eq} \approx 2*r_{o} \$$

Then, transconductance can be simplified as $$\ g_{m,eq} \approx \sqrt{2 \mu_n C_{ox,eq} (\frac{W_{eq}}{L_{eq}}) I_D} \$$

With :

• $$\ L_{eq} = 2L \$$
• $$\ C_{ox,eq} = 2C_{ox} \$$ since we doubled the area of the gate = W*2L

We can conclude that $$\ g_{m,eq} \approx g_{m} \$$

And thus, the 2 stacked-up mosfets would have double the Gain : $$\ G_{eq} \approx 2*G \$$.

Why is M1 in triode region?

Why is M2 in saturation region?

I am going to simulate this circuit during the weekend and update my post accordingly. But if it's the case, why is the gain $$\ G_{eq} = g_{m1}*(r_{o1}+r_{o2}) \$$ ?

Shouldn't M1 be in saturation while M2 should be in the triode region acting as a Drain resistor for M1. (According to the gain you've found)

• I've wanted to post a comment 1st, but i don't have enough reputation to do so. So I've posted an answer where we can discuss :) Commented Jul 29, 2022 at 17:00
• Thanks for the help! I wasn't expecting to combine the two transistors. Can you do that when they are in different operating regions? I believe my gain is incorrect as my math is wrong. M2 is in saturation and M1 is in triode region but I have no idea why. I was thinking that this might be solved with more of a small signal model analysis approach. This circuit should be similar to a cascode amplifier. Commented Jul 30, 2022 at 4:30
• @Jirhska Well, my logic of combining the two transistors is completely wrong since the intrinsic Gain (As I've found in simulation) is not double the gain but rather its square : so, basically a cascode. M1 is indeed in triode region if M2 is in saturation. I am still tryin to figure out why M1 is in triode region thought. I am writing another answer with my findings. I'll delete this answer once you've seen this comment Commented Jul 31, 2022 at 21:07
• I have to review the problem a little bit more, but thanks for all your help. However if we assume M1 is in saturation then VDs1 >= Vgs1-Vt. So lets say VDs1 = Vgs1-Vt to be in saturation. We go to M2 now and test what is going on. Because the gates are connected Vgs1= Vg2. Vgs2 = Vgs1- VDs1. Then testing gate-source minus threshold: Vgs2-Vt then reduces to Vgs1-Vgs1-Vt. This is less than zero so M2 is not even ON! So therefore our initial guess of M1 being in saturation is incorrect. M1 has to be in triode. Commented Aug 1, 2022 at 3:12