# How to generate a single pulse signal with existing clock signal

There are 2 input signals to the circuit.
one is the clock signal of 1MHZ.
the other one is the 'input'.

Making use the clock signal, how do I generate a single pulse when the input signal changes from low to high, with appropriate circuit.

• Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking.
– Community Bot
Jul 31, 2022 at 1:52
• ok, let me modify the question Jul 31, 2022 at 1:57
• Jul 31, 2022 at 2:25
• What is the technology you're working with? PLC? Discrete logic - if so, what family? PLD? FPGA? Without this important detail, the question is too broad and off-topic here. Jul 31, 2022 at 3:45
• Assuming the clock is faster than input pulse width, It's a simple positive edge detector. You need an AND gate a D flop. Jul 31, 2022 at 6:22

To begin with, you could AND the input signal with the clock signal to get a gated clock signal. Then you could use a negative-edge-triggered, D-type flip-flop clocked from the gated clock signal to detect the first falling edge of the gated clock and clear its $$\\overline{Q}\$$ output.
The $$\\overline{Q}\$$ output could then AND with the gated clock signal resulting in a single pulse (what you want).