There are 2 input signals to the circuit.
one is the clock signal of 1MHZ.
the other one is the 'input'.

Making use the clock signal, how do I generate a single pulse when the input signal changes from low to high, with appropriate circuit.
enter image description here

  • 1
    \$\begingroup\$ Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking. \$\endgroup\$
    – Community Bot
    Jul 31, 2022 at 1:52
  • \$\begingroup\$ ok, let me modify the question \$\endgroup\$
    – kintaro
    Jul 31, 2022 at 1:57
  • \$\begingroup\$ See: vhdlguide.com/2016/07/23/edge-detector \$\endgroup\$ Jul 31, 2022 at 2:25
  • \$\begingroup\$ What is the technology you're working with? PLC? Discrete logic - if so, what family? PLD? FPGA? Without this important detail, the question is too broad and off-topic here. \$\endgroup\$ Jul 31, 2022 at 3:45
  • \$\begingroup\$ Assuming the clock is faster than input pulse width, It's a simple positive edge detector. You need an AND gate a D flop. \$\endgroup\$
    – Mitu Raj
    Jul 31, 2022 at 6:22

1 Answer 1


To begin with, you could AND the input signal with the clock signal to get a gated clock signal. Then you could use a negative-edge-triggered, D-type flip-flop clocked from the gated clock signal to detect the first falling edge of the gated clock and clear its \$\overline{Q}\$ output.

The \$\overline{Q}\$ output could then AND with the gated clock signal resulting in a single pulse (what you want).

enter image description here

  • OUT1 is the gated clock
  • OUT2 is the end-of-first-pulse detector
  • OUT3 is, I believe what you might want

But there are other things to consider that you haven't mentioned in your question such as what happens when the input signal goes low again and returns high - maybe you don't want another pulse to be generated or, maybe you do? You need to address this if you want a proper answer.

You also should consider that the input signal might not be synchronous with the clock signal and, the pulse produced could be very thin and cause problems: -

enter image description here


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