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Objective

To achieve a 12-hour interval between 30-minute runs (on for 30 minutes, off for 12 hours).

Circuit

On (foolishly) thinking that this would be implemented more simply using discrete ICs as compared to an MCU, I chose the CD4060 for long delay timing and the CD4001 quad-NOR acting as an SR latch. Below is the circuit diagram rendered in Falstad's simulator (CD4001 on the left, CD4060 on the right):

aforementioned circuit diagram

Both 10 µF capacitors in the circuit are X5R MLCCs; the resistors are all 600 mW 1%.

In short, the intended mode of operation is as follows, starting after a RESET by pushbutton is initiated:

  1. RESET is pressed. CD4060 is reset, and CD4001 SR latch is latched high.
  2. CD4060 reaches Q9 (256 clock pulses), triggering SR latch reset to low.
  3. CD4060 reaches Q14 (8192 clock pulses), triggering SR latch set to high.
  4. CD4060's Q14 pulse is fed back to its own reset pin, resetting the chip and restarting the cycle.

Note the transistor-RC element in between Q14 and the SR latch set. This was the product of me thinking the duration that Q14 was on to the time it got reset was insufficiently long to trigger the SR latch, but it turns out that was also not the issue.

Tests

A selection detailing the wild goose chase I have led on:

  1. Checked 30-minute functionality of Ct = 10 µF and Rt = 240 kΩ. Works as expected; SR latched low after that time.
  2. Checked 12-hour functionality of Ct = 10 µF and Rt = 240 kΩ. CD4060 resets, but the SR latch didn't reset to low. (This is the problem.)
  3. Set Ct = 100 pF with Rt = 240 kΩ to observe if cycle repeat occurred in reasonable timeframe. Behavior is as expected and the cycle repeats endlessly, therefore ruling out the board, contacts, and chips as error sources.
  4. Set Ct = 10 nF with Rt = 240 kΩ for same reason as (3). Cycle also repeats just fine.
  5. Set Ct = 10 µF with Rt = 10 kΩ (about 30 minutes for the whole cycle to complete). Stages (1), (2), and (4) function correctly, but (3) does not occur even though the CD4060 reset, indicating presence of a pulse on the line.

Unfortunately, I'm just a hobbyist and don't have access to an oscilloscope, so I've had to do just empirical tests with LEDs (driven by 2N3904 transistors to prevent loading down of outputs).

Outcome

  • Why does the cycle not repeat when Rt = 240 kΩ and Ct = 10 µF?
  • In test (5), why did the CD4001 not trigger even with the line pulse?

I have been thoroughly stumped by this for a few days in trying to figure out why it doesn't work under the conditions designed in the circuit. Hoping that this community can shed some light on this for me, and possibly some ways to go about rectifying the issue.

I may end up going with the microcontrollers, but I'm really quite interested (and invested) in learning more about why this circuit doesn't seem to work as it should. Thanks!

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  • \$\begingroup\$ Connect Q9 directly to D2 because Q9 is high and goes low just at rising Q14. The introduced delay by the 100k resistor may be too long \$\endgroup\$
    – Jens
    Jul 31 at 20:38
  • \$\begingroup\$ Thanks for the suggestion, I'll give that a try and report back in a bit! I'm curious, would the delay caused by the 100k resistor be present as well for Ct = 10 nF? If so, why does that Ct value not experience the same failure? \$\endgroup\$ Jul 31 at 20:55
  • \$\begingroup\$ Post a picture of the circuit. A build issue can be the cause of weird issues. \$\endgroup\$
    – Mattman944
    Jul 31 at 22:33
  • \$\begingroup\$ @Jens I tried tying Q9 directly to D2, but the issue persists. Think I'll try another approach. Thanks for the input! \$\endgroup\$ Aug 1 at 18:14
  • \$\begingroup\$ @Mattman944 The circuit was tested at other Ct values and found to be functional, so we believe the issue is either a CD4001 or more likely, CD4060-related quirk (probably the reset voltage threshold). I'll try out James' answer below and if that doesn't work I'll add an image. Thanks \$\endgroup\$ Aug 1 at 18:16

1 Answer 1

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I think you should get more success with this circuit. The 4060's reset signal comes from the output of the latch ensuring that the latch actually latches before resetting the 4060.

When Q14 goes high, the output of IC2a also goes high and the RC circuit generates a short high going pulse to reset the 4060. The diode prevents the 4060's reset input being taken too far negative when the output of IC2a returns low.

Timer

Also I've experienced problems in the past using such a high value resistor as that 2M resistor in that position. I would suggest reducing it to 470k.

EDIT

The circuit below makes use of the other two nor gates in the 4001 to add a power-on-reset function and a reset by push-to-make switch. I haven't tested it but the theory of the circuit seems sound.

Timer with reset

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  • \$\begingroup\$ Thanks for the detailed response! Not sure why I didn't think of using the latch output to reset the 4060; in hindsight it seems so clear. By the way, what sort of issues did you experience when using 2 MΩ for Rclk? \$\endgroup\$ Aug 1 at 18:19
  • \$\begingroup\$ @perhapsmaybeharry I ended up with a jittery clock waveform rather than a clean signal. \$\endgroup\$
    – James
    Aug 1 at 18:23

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