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I'm trying to understand the circuit design from this application note.

Here is the figure:

enter image description here

The author said:

Resistor RIN provides a dc return path for the VS/2 reference voltage and sets the circuit’s AC input impedance. The RA/RB voltage divider adds considerable resistance in series with the op amp’s positive input terminal, equal to the parallel combination of the two resistors.

I'm confused about what the "DC return path" means, and how to calculate the equivalent resistor of the voltage-dividing network.

I would also like to know what the function is of the capacitor in series with the resistor connected to ground.

enter image description here

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    \$\begingroup\$ Your question about the single supply circuit should be left to another question. Please edit your post to limit it to the one circuit. \$\endgroup\$
    – Null
    Aug 2 at 13:37

2 Answers 2

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The answer is simple - and the reason for the input circuitry (and the cap C1) is the fact that the circuit has single supply. This fact has three consequences:

1.) The pos. opamp input must be biased at app. half of the supply voltage Vss (resistors RA and RB) - thus ensuring that the DC bias point is app. in the middle of the linear input-output transfer curve.

2.) Because of this DC bias at the pos. input terminal the input signal must be applied through a capacitor Cin. At the same time an additional resistor Rin is used to keep the input resistance at a high value of 100 kOhms (because the midpoint between RA and RB is ac-wise grounded via C2).

3.) To keep the output of the opamp at a DC bias of Vcc/2 the DC gain must be limited to Adc=1. This requires 100% feedback for DC (no DC current through R2) - and this is accomplished using the capacitor C1. Independent on this, the ac closed-loop gain (above the corresponding lowpass corner frequency) can be selected as Acl=1+R2/R1.

Comment: Of course, the above assumes that the opamp can be treated as ideal (no input currents into the opamp input terminals and infinite open-loop gain Aol)

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  • \$\begingroup\$ Thank for your reply, but how can I get an in-depth understanding of these op-amp circuits? Are there any books or resources to recommend? \$\endgroup\$
    – Kituro Lin
    Aug 5 at 12:46
  • \$\begingroup\$ Of course, there are many. One of my favourites: Sergio Franco: "Design with Operational Amplifiers and Analog Integrated Circuits" (Mc Graw Hill) \$\endgroup\$
    – LvW
    Aug 5 at 14:19
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All op amps have a small bias current flowing into or out of their input terminals, for some op amps this is a very small current indeed. To enable the op amp to perform correctly, the circuitry connected to the op amp's input terminals must provide a path for these input bias currents to flow to ground, otherwise known as "a dc path to ground".

Capacitors block dc current and therefore there is no dc path to ground through Cin but the input bias current can flow to ground via Rin and RB keeping the op amp happy.

C2 presents as a low impedance at the node in between RA and RB, effectively creating a low impedance node in between RA and RB. This means that above a certain signal frequency, where C2 has low impedance, the input resistance "seen" by Cin will be approximately Rin (100k). At these higher frequencies there will be very little voltage ripple at the node between RA and RB. As signal frequency decreases, the impedance of C2 will increase, the input impedance that Cin "sees" will increase above the value of Rin. When the signal frequency is high enough, C2 effectively by-passes RA and RB much like the action of the emitter resistor by-pass capacitor in a common emitter amplifier. Almost all the signal amplitude appears across Rin, the 100k resistor.

An advantage of having that configuration is that C2 in conjunction with RA and RB can filter out noise on the power rail and reduce the chances of noise appearing at the op amp's positive input.

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