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Say I have a D Flip Flop and I have a resistor, capacitor, diode, and Schmitt buffer to keep its reset line low for a few ms during startup (as per this answer)

This takes care of power-on, but during operation of the circuit if I need to drive reset low, how can I do it? The Schmitt buffer is already driving that pin to a logic high - I suppose one thought is to insert a series resistor between the Schmitt buffer and Reset pin, then drive a low-side FET in order to pull Reset low when desired. Is this the best way to do it, or am I missing some better solution?

schematic

simulate this circuit – Schematic created using CircuitLab

Note: I'm aware the schematic shows an SR latch - the DFF component didn't show a Reset pin and I'm generally unfamiliar with the schematic tool, sorry!

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    \$\begingroup\$ If the DFF's RESET is active-low then yes, it's the simplest yet a good enough solution. A better solution may include glitch removal in case a mechanical button used instead of GPIO. \$\endgroup\$ Aug 2 at 14:44
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    \$\begingroup\$ That would work. Or you can put your transistor right at the input to the SCHMT if you want. Maybe add a 100 Ohm in series with the transistor to avoid over-stressing it. \$\endgroup\$
    – mkeith
    Aug 2 at 16:04
  • \$\begingroup\$ Why do you need to drive reset low? For what chip this is? I ask for further info because the specific case you have can have a specific way of solving it. \$\endgroup\$
    – Justme
    Aug 2 at 17:14
  • \$\begingroup\$ Most microcontroller GPIO ports are set to high impedance/input on startup. So can't you just use a pull-down resistor to keep the flip flop reset line low during startup after which the software can take control and set the GPIO pin to output ?... \$\endgroup\$ Aug 2 at 17:20
  • \$\begingroup\$ Looks good..... \$\endgroup\$
    – Mitu Raj
    Aug 2 at 19:14

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The reset circuit works by charging the capacitor through a resistor until it reaches a voltage that will toggle the Schmitt buffer output high. The voltage on the capacitor then stays high enough to keep it in this state until the capacitor is discharged.

So you could just put the FET across the capacitor to discharge it. This way you don't have to worry about the buffer trying to drive the reset through a high resistance.

As mkeith points out it would be a good idea to add a resistor between the capacitor and transistor to limit the discharge current.

The only problem with doing it this way is that there will be the delay when you want to un-assert reset. Whether this is a problem or not would depend on your use case.

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    \$\begingroup\$ I think it would be OK to directly short the cap with a transistor because it is a small cap. But it might not be a bad idea to just put a 100 Ohm resistor in series with the FET to avoid excessive current during discharge. \$\endgroup\$
    – mkeith
    Aug 2 at 16:06
  • \$\begingroup\$ Good thought! I think if adding an extra resistor anyway, I may stick with the circuit proposed in the original post to avoid that delay. If I understand correctly, I could even use this circuit to assert Reset of every active low device in the entire board at startup, and then control them during run-time with one extra resistor + FET per device (?). In any case, the reassurance from your answer and others' comments makes me feel a lot better about this, thank you! \$\endgroup\$
    – Orotavia
    Aug 3 at 0:11

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