Taking a look at the block diagram for a half-bridge gate driver, the high-side gate voltage is run through the bootstrap diode which would cause a voltage drop, while the low side has no such diode.

So are the gate voltages different between the high side and the low side? I would expect the high side gate to be driven at a lower voltage.

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Edit: My application is adapting a DRV8600 gate driver to control the EPC2065 GaN FET, which is driven off of a 5-6 V gate voltage, so this would be a problem for me.

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    \$\begingroup\$ I guess you're right, but it should not be significant if gate voltage is chosen with ample margin. \$\endgroup\$ Aug 2, 2022 at 16:49
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    \$\begingroup\$ Or it's driven with extra, because the switch node dips below GND momentarily during commutation, and no series resistance or inductance is shown in the bootstrap charging path. As is so often the case: it depends! \$\endgroup\$ Aug 2, 2022 at 17:47
  • \$\begingroup\$ That MOSFET epc-co.com/epc/Portals/0/epc/documents/datasheets/… has a typical gate threshold of just 1.2V (max 2.5V) and the curves show adequate performance for gate drive 4-5V. You can add another diode for the low side so both devices will see no more than 5.5V with a 6V Gvdd supply. \$\endgroup\$
    – PStechPaul
    Aug 2, 2022 at 21:05
  • \$\begingroup\$ I can't find a DRV8600 driver, but there is a ti.com/lit/ds/symlink/… that looks very similar. It's helpful to add links to any special parts like this. \$\endgroup\$
    – PStechPaul
    Aug 2, 2022 at 21:41

3 Answers 3


the high side gate voltage is run through the bootstrap diode which would cause a voltage drop

So-what if a diode drop is caused; anybody designing a low-side driver would make sure that the power rail is a volt or two higher than what is needed and, the same applies for the high-side (minus one diode drop).

I would expect the high side gate to be driven at a lower voltage

Yes, but, as designers we make sure that the loss due to one diode-drop is insignificant.

  • \$\begingroup\$ For context, I am trying to adapt a DRV8300 mosfet driver to drive EPC2065 Ganfet which has a 5-6V gate voltage range. So in my case, even a 1V or 0.5V drop may significantly change the performance? \$\endgroup\$ Aug 2, 2022 at 17:20
  • \$\begingroup\$ @TannerBeard yes, that is a problem. I have also used a similar device (EPS2037) in a high-side situation and decided not to use a bootstrapping circuit but an isolated DC-DC converter. Maybe if you properly regulate your GVdd to 6 volts you should be good to go. I didn't have that luxury!! \$\endgroup\$
    – Andy aka
    Aug 2, 2022 at 18:35
  • \$\begingroup\$ I saw in EPC's video youtu.be/K6sAmYt0wx4?t=1107, where they used a zener diode to get the regulation to not go above 5.2v. Maybe just use 5.5v supply and a 5.2v zener on both high side and low side? Seems super hacky though \$\endgroup\$ Aug 2, 2022 at 20:45
  • \$\begingroup\$ I ended up using a 5.1 volt zener on the output of my DC-to-DC converter just for peace of mind. So, I reckon it's not too hacky @TannerBeard \$\endgroup\$
    – Andy aka
    Aug 2, 2022 at 21:51

Consider what happens to \$C_{BSTA}\$ when the top leg's lower FET is enabled:

  • \$GLA\$ goes high with respect to ground, so \$R_{GLA}\$ is energized and the lower FET conducts, since it's source is connected to ground and gate is now a positive voltage.
  • \$SHA\$ goes to ground level now, since the lower FET source and drain are essentially connected.
  • \$GVDD\$ flows through \$GVDD\$ diode, charging \$C_{BSTA}\$ to \$GVDD\$ minus one diode drop.
  • Now once \$GLA\$ goes low, deadtime happens, and \$GHA\$ goes high, \$C_{BSTA}\$ is still charged to \$GVDD\$ minus one diode drop.
  • So \$GHA\$ is high, \$R_{GHA}\$ is energized, and \$PVDD\$ is connected to SHA.
  • This cap powers the gate driver "above" whatever the SHA voltage is (\$PVDD\$), ensuring that the high NE-FET will actually be turned fully "on" by a positive voltage.
  • The \$GDVD\$ diode prevents this higher voltage from flowing into other circuitry (it is now reverse-biased, so this current only flows into HS.)
  • The cycle repeats.

So yes, the high-side gate is generally about one diode-drop (0.7 V) lower due to this diode. This is measuring from the gate to the source pins, so-called \$V_{GS}\$. And it has to be, since the only thing that will "turn on" a N-E-MOS is \$V_{GS}\$. Note that, if you 'scoped from ground to the low FETs, you'd see 0-5v on those gates, and anything from 0 V to \$PVDD\$ + \$C_{BSTA}\$ - 0.7V or so on the high gates.

The boost capacitor must be sized to the FET gate capacitance, such that it supplies enough current to sufficiently charge the gate before running out of juice. If the value is too small, the relative voltages reached will be far lower and the FET may not fully turn on, resulting in excessive power dissipation at best. And it can't be too large, else the (increasing) pulse current could destroy the gate outright and/or \$GVDD\$ diode (mainly through thermal failure, shorted, which then causes the whole chip to fail.)

If attempting to replace a MOSFET with an IGBT or other exotic device, this can be a slippery slope due to many small parasitic changes between the parts. At low frequencies these are much less an issue. But when switching square-waves at any appreciable speed, parasitics like Miller Capacitance, lead inductance, voltage knee differences (lots of things) could manifest entirely new issues.

In that case, heavy use of the 'scope and a gentle, methodical mindset could help. Uncharted territory ahead! A balance of calculation and experimentation may be in order. Or try to find a recommended driver, example circuit, dev board etc. for your GaN device (or similar device) showing what parts they chose.

  • \$\begingroup\$ Thank you so much for the insightful reply! A couple of questions: when you say "appreciable speed" what kinds of speeds are you talking? I will be running at 24khz-96khz. Also, when you say that a larger boostrap capacitor shouldn't be used because of high pulse currents, won't the current be the same regardless of the size due to the resistance of the ganfet gate (Rg)? \$\endgroup\$ Aug 2, 2022 at 20:54
  • \$\begingroup\$ Some gate driver circuits recommend a resistor in series with the diode to the boost capacitor to limit the current, but it appears that this circuit is contained within the driver module. It could be placed in series with the external capacitor, but that would limit the available surge current for the gate. Maybe a diode across the resistor? \$\endgroup\$
    – PStechPaul
    Aug 2, 2022 at 21:34
  • \$\begingroup\$ The problem with squarewaves is that they are comprised of harmonics. The more "square" and faster the transitions, the higher the harmonic range. So a very strong and clean (desired) squarewave at 100kHz could have significant harmonic content in the tens of MHz range, and a small component in the hundreds of MHz. So if a gate resistor is used, this obviously slows down these transitions which reduces harmonic extent, at the expense of increased power loss from slower switching. \$\endgroup\$
    – rdtsc
    Aug 3, 2022 at 12:52

Here is the response from the EPC Corporation (manufacturer of the GaNFets in this circuit)

A voltage drop would occur, but there is a nice cancellation of the drops in 2 of the diodes, resulting in the upper gate drive being approximately the same as the bottom:

  1. As you mentioned, the top boost diode, Dbstst, drops voltage. So, the output is about 5V – 0.7 V = 4.3 V.
  2. But, the reference point of the upper gate drive is the switch node. And, during the dead times, the bottom FET’s body diode (and, in this case, the parallel diode Dap) have a drop. So, during the dead time the switch node is below ground. About 1 V below ground in this case.
    These diode drops offset each other. Resulting in the upper gate drive voltage in many cases being the same or even higher than the bottom gate driver voltage. The Zener Dclmp helps in case the upper gate voltage floats too high.

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