Via stitching in PCB design

Question

I am a newbie in PCB designing and started designing PCBs recently. I came across a concept called via stitching which is to achieve increased current carrying capacity of the board. I looked for the references on the internet but did not find the ones which will clear the doubts that I had. The doubts that I have regarding the via stitching are:

1. If adding vias is intended for increased current capacity then what number of vias should be added and what should be its diameter?
2. If there is not enough space to add bigger diameter vias, then can a large number of small-sized vias be used?
3. Is there any calculation regarding the number of vias we need to put for a specific current requirement?
4. Is there any guidelines regarding the clearances between each via if we have space constraints?

---

It is true that the board layout depends on our application. My design is a two-layer board and I have added separate power planes on both layers for high-current carrying components. Do I need to add vias there to connect the power planes on both layers (the components are through-hole)? And in case we are adding vias to connect multiple power planes, then will it be a good idea to stitch multiple vias to give more buffer to the board's current carrying capacity?

Answer 1

The current carrying capacity of a via is covered in the IPC-2152 standard. The suggestion to download the Saturn PCB toolkit is a good one because it has a calculator which allows you to play around with the parameters. Please note, a more conservative number for the via plating thickness is 0.02 mm (IPC-6012A standard, Table 3-1).

In general, the current carrying capacity of a via is proportional to the square root of the drill diameter. For example, a 0.25 mm drill in a 1.5 mm thick FR-4 PCB with a plating thickness of 0.02 mm can carry 1.1 A with a 10 °C rise.

If you double the drill diameter (to 0.5 mm), the via can carry 1.6 A. So two vias with a 0.25 mm drill can carry more current than one 0.5 mm drill via.

Does this mean that two small vias take up board space? Not necessarily. Once you take into account the pad diameter (IPC-2221A standard, section 9.1.1) and the electrical clearance requirements (IPC-2221A standard, Tale 6-1), two smaller vias can take up more board space than one big via. That being said, it's sometimes easier to find the space to fit a few small vias than one big one.

Unfortunately, the answers to most of your questions depend on the application. In regards to the last question, I've had different fabricators give me different answers regard the minimum via to via spacing. If you have a fabricator in mind, they can tell you the minimum spacing they are comfortable with.