I want to interface an ADC with an FPGA but I'm confused with some basic terminologies. What is the relation between ADC sampling rate and the output data rate of ADC? For example, if ADC sampling rate is 100Hz does that mean it outputs 100 digital values/sec? Also, is there a problem if clocks are not matched? For example, the ADC has 500MHz sampling rate/frequency whereas my FPGA can run at a maximum of 100MHz. What is the relation between ADC sampling rate and FPGA clock frequency? Thanks.

  • 4
    \$\begingroup\$ It depends entirely on the specific device i.e. serial vs parallel bus has completely different numbers AND sampling frequency has very little to do with output bit-rate for a serial device. But, some devices will be odd-ball exceptions so, pick your device and leave a data sheet link. \$\endgroup\$
    – Andy aka
    Aug 3 at 13:26

1 Answer 1


For example, if ADC sampling rate is 100Hz does that mean it outputs 100 digital values/sec?

Yes, because 'sample' === 'digital value'. However, a 100 Hz sampling ADC is unlikely to require an input clock of 100 Hz, it's likely to be orders of magnitude faster, usually a common MHz crystal frequency. Something that slow will also probably use a serial output, with a bit clock that does not need any specific relationship to anything, as long as it can transfer the samples fast enough.

When an ADC is as quick as 500 MHz, things can be just as complicated. There are many ADCs that would use a sample rate clock input for sampling, though there are some that would take a sub-multiple and multiply it internally. Very old designs of ADCs had parallel data outputs which delivered a word per clock cycle. However these days you're likely to find a very high speed serial interface, JESD204B, which uses Gbit rates, with several serial lanes aggregated to get the total data rate (just like PCIe, SATA, HDMI ...). Many FPGAs directly support such high speed interfaces (1), even if their system fabric clock rates are much lower.

If you wanted to interface a 500 MHz ADC with a 100 MHz FPGA, you probably could, if they both had JESD204B interfaces. You would have to implement several parallel flows in the FPGA to handle all of your samples though.

(1) Now they do. When I was working in this field in the 1990s-2000s, a well known ADC company would visit from time to time doing market research, and ask us what we wanted. Every time I would tell them that parallel interfaces took up too much precious board area, and to talk to the FPGA companies and sort something out. Obviously I was pushing at an opening door.

  • \$\begingroup\$ Don't know much about FPGA, but in MCU it is quite common to program ADC for hardware oversampling and shifting, e.g. sample and accumulate at 1kHz, then shift result right by 2 for the actual data rate 250 samples per second. \$\endgroup\$
    – Maple
    Aug 3 at 16:00
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    \$\begingroup\$ @Maple It depends on the processing you want to do. Accumulate and dump works well for simple oversampling to avoid overstressing a small MCU, but if you've paid for 500 MS/s, then you'll at least want to be using a proper decimating filter or digital tuner/downconverter. But with an FPGA, you can do anything. Anything causal that is. So you can run your 500 Ms/s data through 5 parallel 100 MHz FIR filters, but not through IIR filters. \$\endgroup\$
    – Neil_UK
    Aug 3 at 16:46

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