I operate BLDC motor with FOC controller, and attempt to characterize Iq as a function of load/torque.

From FOC theory, I would expect a linear relationship between the torque and the Iq current component.

What I observe is a sign reversal, where Iq goes towards zero as the load (friction) increases, and then changes sign.

In this test, the torque never changes direction, as the speed is held mostly constant by the speed PID loop, and the inertia is negligible.

So what could possibly cause an effect like this ?

(the control is well-tuned, and follows desired speed for a wide range of RPM setpoints and loads)

Edit: There is a load value where the controller reports zero current which is nonphysical (the motor spins, overcomes friction and consumes energy). So I don't see how it can be anything else but an artifact/bug of the FOC algorithm.

current and RPM plot

  • 1
    \$\begingroup\$ Looks like your speed controller is oscillating. When your speed goes above the reference speed, the controller will output potentially a negative Iq reference and so you have this osciallting behaviour as seen in picture 2. Maybe you can give more weight on your I-term of the speed controller? \$\endgroup\$ Commented Aug 3, 2022 at 15:27
  • \$\begingroup\$ Not sure which oscillations are you referring to. The changes in speed in the plot are due to periodic application of a friction brake to demonstrate the effect. \$\endgroup\$
    – vadimus
    Commented Aug 3, 2022 at 15:30
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    \$\begingroup\$ The fact that you are periodically applying a friction brake probably should have been mentioned in the original question. Anyway, the simplest explanation for what you are seeing is that for some reason, there is an offset error in the Iq graph. For whatever reason, the actual Iq is higher than the Iq shown in the graph by roughly 0.25 A or so. \$\endgroup\$
    – user57037
    Commented Aug 3, 2022 at 18:19
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    \$\begingroup\$ If you monitor the phase current with a current probe, Iq should correspond to the peak of the sine wave. This might allow you to determine if there is indeed an offset. \$\endgroup\$
    – user57037
    Commented Aug 3, 2022 at 21:40

1 Answer 1


To answer my own question, the root cause of the effect was a phase current measurement error (as mkeith suggested), due to insufficient filtering of ADC input.

  • \$\begingroup\$ It could also be dependent on the specific implementation of your current sensing. For instance, if you're doing all low side current sensors, the accuracy of your measurement is very dependent on the sampling time relative to the low side FET activation. Also if the ADC channels are collected in sequence, rather than simultaneously, the spread in time across those three can introduce distortions of the synchronous Iq measurement. \$\endgroup\$
    – Ocanath
    Commented Dec 20, 2023 at 19:31

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