3
\$\begingroup\$

I'm currently trying to design a PWM driver for an impedance-mismatched long cable. Sending rectangular pulses (rise-fall time ~0s) over a long cable that is not matched with its impedance results in voltage over and undershoots caused by the reflected wave phenomenon (RWP).

My literature research tells me there are 3 different techniques to mitigate the undesired effects of voltage over and undershoots caused by the RWP \$[1]\$:

  1. Impedance matching filters
  2. Reduction of slope (dv/dt)
  3. Multi-level inverters

I am focussing on 2. and 3. as 1. has the problem that passive filters are bulky, lossy and expensive. (Not suitable)

I dont want to just apply the techniques, but also to understand why and how they work.

The reflection process is often illustrated using bewley diagramms. They certainly have their reason for existence, but for me they were too abstract. I found 2 articles [2, 3] using a different diagram style, that I think gives a very good optical visualization of the RWP:

RWP rectangular pulse

The image above shows the RWP of a rectangular pulse. With transmission delay \$t_d=\frac{l_c}{v_p}\$, cable length \$l_c\$ and velocity wave propagation \${v_p}\$.

Driver-cable reflection coefficient \$Г_D= \frac{Z_D-Z_c}{Z_D+Z_c}\$ and cable-receiver reflection coefficient \$Г_R= \frac{Z_R-Z_c}{Z_R+Z_c}\$.

In words:

a: We send a rectangular pulse of magnitude \$V_{dc}\$ "into" the cable.

b: After \$t_d\$ the pulse has reached the receiver end where it gets reflected. The superposition of forward travelling wave (driver to receiver) and backward travelling wave (receiver to driver) results in a voltage overshoot \$V=V_{dc} * (1 + Г_R)\$.

c, d: Once the reflected wave hits the driver side another reflection happens and the magnitude of the forward travelling wave driven by the driver is reduced, so that the superposition of forward and backward travelling wave reaches \$V_{dc}\$ again.

e: the reduced magnitude forward travelling wave hits the receiver side and gets reflected. The superposition at the receiver end is now below \$V_{dc}\$ and we can observe an undershoot.

f=a: once the reduced magnitude backward travelling wave hits the driver side the driver will ramp up the magnitude of the forward travelling wave to reach a superposition of \$V_{dc}\$. The cycle repeats at step a. This time though the forward travelling wave doesn't have a magnitude of \$V_{dc}\$ but slightly below that: \$V_{forward3} = V_{dc} * (1 - (Г_R - Г_R^2))\$.

Thus the system converges into a stable state after infinite cycles (lossless line) of overshoots followed by undershoots. In practice this happens a lot faster due to cable losses and the over and undershoots get very small very fast, so you cant actually see the reflections even though they are happening.: enter image description here

In the stable state the potential along the complete length of the cable is equal (assumption: lossless line) and is the superposition of a forward and backward travelling wave: \$V_{dc} = V_{forward} * (1 + Г_R)\$

This diagram style can also be used to then analyze how signals with reduced slope can reduce the over and undershoots, but it is very difficult to do this using MS Visio, because of all the edges and angles a trapezoid will produce. Thus I decided to use MATLAB to simulate all of this. This has 2 advantages:

  1. I can feed any signal waveform into the cable (rect, dirac, trapezoid with variable risetime, sine...)
  2. I don't have a few pictures of the reflection process, but a complete animation (video).

So I created a very simple MATLAB model (assumption is a lossless line and a point to point connection). The model takes cable properties (length, impedance propagation delay) and driver+receiver resistance into account (no complex stuff, no inductive/ capacitive couplings between wires etc). It's basically 2 shift registers. 1 right shiftreg for the forward travelling wave, and 1 left shifting for the backward travelling wave. Every loop iteration shifts the upper reg 1 to the right and the lower 1 to the left. The carry of the upper reg gets multiplied by the reflection coeff \$Г_R\$ and fed into the lower reg. Every iteration the 2 registers and their sum (superposition) is plotted. In LTSpice you will only see the superposition of the waves.

enter image description here

You see that currently the driver is loading a rectangular voltage with an amplitude of 1V into the register. 8 more iterations and the pulse has travelled the cable once and reaches the cable end where it gets reflected. Ofc. the real model has significantly larger registers...

Question

Is this model right?

I have used it for the last weeks and I was very happy with the results. They were very similar to the SPICE simulations I performed. (ofc. there were differences because I assumed a lossless line in my model, but used a lossy line in LTSPICE). It helped me understand what is happening and why the reduction of slope is an effective measure to reduce over and undershoots.

Seeing the reflection process and the forward and backward travelling wave in real time one immediately sees that by stimulating the cable not with \$V_{dc}\$ but with an intermediate step of \$V_{step} = \frac{V_{dc}} {1+Г_R}\$ for a duration of \$t = 2 * t_d\$ produces good results, because the superposition of \$V_{step}\$ and its reflection result in \$V_{dc}\$ across the cable after just \$2 * t_d\$.

A colleague of me told me that the model is wrong. Reflections only happen during the transitions, whereas my model assumes that reflection always happen, even during the steady state of the signal, it's just that the superposition of the forward and backward travelling wave is stable.

Where is my mistake? How would I need to adapt my model and my understanding to grasp what is really happening when charging a transmission line? When does the last reflection occur? Why are there no reflections during the steady state? Even during the steady state the driver needs to push current into the cable (assuming it has a resistive load attached), doesnt that mean we have a wave?

I can't attach videos of the MATLAB simulations, so I uploaded 2 videos to youtube (watch on 2x speed):

Rectangular pulse: https://youtu.be/TFdFd7YVYvs

Trapezoid \$t_{rise}\$ = \$3 * t_d\$ :https://youtu.be/3WymcupIZ1w

EDIT

MATLAB modell results in timedomain: enter image description here

Sources

1 J. He, G. Y. Sizov, P. Zhang and N. A. O. Demerdash, "A review of mitigation methods for overvoltage in long-cable-fed PWM AC drives," 2011 IEEE Energy Conversion Congress and Exposition, 2011, pp. 2160-2166, doi: 10.1109/ECCE.2011.6064054.

2A. von Jouanne and P. N. Enjeti, "Design considerations for an inverter output filter to mitigate the effects of long motor leads in ASD applications," in IEEE Transactions on Industry Applications, vol. 33, no. 5, pp. 1138-1145, Sept.-Oct. 1997, doi: 10.1109/28.633789. Figure 2.

3 A. von Jouanne, P. Enjeti and W. Gray, "The effect of long motor leads on PWM inverter fed AC motor drive systems," Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95, 1995, pp. 592-597 vol.2, doi: 10.1109/APEC.1995.469081. figure 5.

1995.

\$\endgroup\$
13
  • 1
    \$\begingroup\$ Your question: Is this model right? your next question: Where is my mistake? - my conclusion is that you have answered your own question. \$\endgroup\$
    – Andy aka
    Aug 3, 2022 at 18:10
  • \$\begingroup\$ “A colleague of me told me that the model is wrong. Reflections only happen during the transitions, whereas my model assumes that reflection always happen, even during the steady state of the signal, it's just that the superposition of the forward and backward travelling wave is stable.“ - if you review it from the point of impedance, your question is answered. It’s mainly a frequency thing. \$\endgroup\$
    – RemyHx
    Aug 3, 2022 at 18:20
  • 1
    \$\begingroup\$ @RemyHx I am afraid I dont understand your answer. Looking at the reflection factor I cannot see any frequency dependency. In my understanding every wave, no matter how high or low its frequency, will get refelcted at an impedance mismatch. The reason why one usually ignores that and only looks at frequencies that have a wavelength comparable to the cable length is, that low frequency signals have such a slow risetime, that multiple reflections are happening while the signal is still rising, thus resulting in no undershoot. This is basically the mitigation technique "reduction of slope". \$\endgroup\$
    – Kilian
    Aug 3, 2022 at 19:20
  • 1
    \$\begingroup\$ I would say that for the purpose of modelling it doesn't matter. The reflection of a steady state is a steady state, so who cares whether you get that steady state by reflecting the one you are receiving, or by generating it from scratch? \$\endgroup\$
    – user253751
    Aug 3, 2022 at 19:26
  • 1
    \$\begingroup\$ @kilian you can terminate at the driver and have no termination at the receiver if you want and, you'll get no data corruption. In fact, I would say, driver-end termination IS THE commonest method for data transmission. Regarding where you model may be wrong, it's the usual case that when you get to complicated stuff like t-lines, it's too much of an ask to get someone to knock-down your previously held belief. Trust in the simulation and you can sim a lossless line no problem <-- use it as the basis for figuring out where your model is wrong. \$\endgroup\$
    – Andy aka
    Aug 3, 2022 at 19:48

1 Answer 1

1
\$\begingroup\$

As @Andyaka and @hacktastical pointed out in their answer,
driver impedance "termination" is a "must".

BERGERON CHART for linear and non-linear systems.

Ideal line.
Here is what you get in three configurations (examples), one is not really "useful" (inductive load).
Wave period = 20 us.

enter image description here

One can see that "wave" is not "distorted", only peak voltage is "different" (Vout and Vout2).

And here is the simulation (example) with a lossy line (with G=0).
Adapting at the driver is "useful" (excepted Inductor load).

enter image description here

Note the change of resistor at input and output ("best" case). EE&O

\$\endgroup\$
3
  • \$\begingroup\$ First of all I want to thank you all for the input you have given me so far. Regarding the suggestion of using a driver output resitor equal to \$Z_c\$: I see that this works great in reducing the over and undershoots, but we can also see the downside: the voltage divider created reduces the voltage delivered to the receiver (resistor, not C or L) and is prohibitive from the point of power efficiency, as we are loosing power in the driver output resistor. This may still be acceptable, but another downside is, that this produces good results only for point to point connections. \$\endgroup\$
    – Kilian
    Aug 4, 2022 at 15:24
  • \$\begingroup\$ If we are looking at a bus topology with a long cable and multiple receivers along the cable, only the last receiver will detect a good rectangular pulse. The other receivers will see an intermediary voltage step in the rising edge. Depending on the receiver design, this may cause unwanted behaviour. The Bergeron chart looks interesting, I havent seen that one before. Thanks for sharing. \$\endgroup\$
    – Kilian
    Aug 4, 2022 at 15:29
  • 1
    \$\begingroup\$ Right for the loss of power when we match at the driver. It is the "problem" for transmission lines"... If well applied, Bergeron can "predict" in the case of non-linear impedance. > only the last receiver will detect a good rectangular pulse. <. I think no for a "receiver", if it is high impedance ... Anyway, good job with MATLAB. \$\endgroup\$
    – Antonio51
    Aug 4, 2022 at 16:37

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.