Is there any advantage to specifying the
range of an integer in VHDL? I know an integer is 32-bit by default.
For example, two counters that will only ever count up to eight (suppose the logic prevents them from going above this number):
signal counter1 : integer range 0 to 8; signal counter2 : integer;
Won't the tools just optimize the unused bits away in either case according to the logic? So if
counter2 both only count up to eight then the
range command seems pointless.
I only see potential downsides in using "range" (for example I had this problem when I used the "range" command but my range was off by one accidentally). Simulation ignores the "range" you give an integer so if you give it the wrong range then you won't notice this in simulation.