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Is there any advantage to specifying the range of an integer in VHDL? I know an integer is 32-bit by default.

For example, two counters that will only ever count up to eight (suppose the logic prevents them from going above this number):

signal counter1 : integer range 0 to 8;
signal counter2 : integer;

Won't the tools just optimize the unused bits away in either case according to the logic? So if counter1 and counter2 both only count up to eight then the range command seems pointless.

I only see potential downsides in using "range" (for example I had this problem when I used the "range" command but my range was off by one accidentally). Simulation ignores the "range" you give an integer so if you give it the wrong range then you won't notice this in simulation.

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    \$\begingroup\$ "I only see potential downsides in using "range" (for example I had this problem when I used the "range" command but my range was off by one accidentally)." That's a benefit, not a downside. It was protecting you from yourself. \$\endgroup\$
    – DKNguyen
    Commented Aug 4, 2022 at 20:22
  • \$\begingroup\$ Range can be used to verify the simulation with designer's intend. Suppose there was a counter whose value should never overflow above 255 by design spec, but if it ever goes beyond for some stimuli, it will be caught in simulation as error. Thus you can verify that your design has a bug. Whether synthesiser will optimise differently with or without range is another story. It depends on how you use the counter in the RTL. \$\endgroup\$
    – Mitu Raj
    Commented Aug 4, 2022 at 20:40

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Always specify a range for all natural and integer items, be they signals, variables, ports or generics.

A primary benefit of using a high-level language like VHDL is that the language stops you entering faulty or unwanted data and behaviour. It gets discovered at compilation time, rather than at run-time.

Range-limited values going out of range will cause errors in simulation. This might happen in compilation, might be at run-time. And all designs should be proven in simulation before synthesis, even if it's only basic testing or to observe the signal behaviour.

As an aside, I always use natural wherever possible instead of integer.

natural is a range-limited subtype of integer that can only hold positive values. That also does range limiting because the subtype natural accepts only the positive range of integer.

I find natural strengthens the design, particularly as most designs have a lot of (often all) scalar types that are only positive. All functions you'll encounter operating on integer will work just fine on natural. That might spark some debate but I've done it with great success on all my designs for decades.

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    \$\begingroup\$ Great answer! I would add that using range-limited values for generics can also be an good way to enforce valid (tested) values. \$\endgroup\$
    – scary_jeff
    Commented Aug 5, 2022 at 7:24

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