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I saw the following instantiation in a Verilog testbench:

`define width 8 

    ......

scale_mux #(`width) m1 (.out(out), .sel(sel), .b(b), .a(a));

I don't know what the "#" means here. Does it replace the parameter declared in scale_mux module with the parameter "width" in test bench? Or does it mean instantiating the scale_mux module 8 times?

The description of scale_mux is as follows:

module scale_mux (out, sel, b, a); 
parameter size = 1; 

output [size-1:0] out; 
input [size-1:0] b, a; 
input sel; 

assign out = (!sel) ? a : 
             (sel)  ? b : 
             {size{1'bx}}; 

endmodule
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1 Answer 1

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Well, after some searching, I found a possible explanation:

When we want to instantiate a Verilog module with parameter, like this:

module scale_mux (out, sel, b, a); 
parameter size = 1; 

output [size-1:0] out; 
input [size-1:0] b, a; 
input sel; 

assign out = (!sel) ? a : 
                           (sel)  ? b : 
                           {size{1'bx}}; 

endmodule

The parameter here is size = 1.

Instantiating this module like this:

scale_mux #(`width) m1 (.out(out), .sel(sel), .b(b), .a(a));

is equivalent to

scale_mux #(.size(8)) m1 (.out(out), .sel(sel), .b(b), .a(a));

So it is to override the parameter, not copying the referred module 8 times.

REFERENCE:

1.https://fpgatutorial.com/verilog-generate/

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