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I am dealing with an old circuit which has 2 shift registers in series and suppose to output 16 different values using SPI. The logic behind this circuit is a bit strange to me and I have a hard time understanding it.

The circuit looks like to be parallel in serial out.

The circuit

I have used shift registers before, but only as a target for writing (e.g. control 8 LED over one SPI line... very easy, I just shifted in a byte and the LEDs where the byte had a 1 at that position would turn on.

But the above circuit, is a different thing I guess. For one, What are the SLOAD and RCK pins doing in this circuit? What happens if I ignore those pins? I just want to read all the 16 bits over SPI.

The other thing, why are there pull-ups for each input of the shift register? Does this mean the ouputs are 1 when the input of shift register is 0?

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  • \$\begingroup\$ The datasheet is readily online. You have the schematic. There are several different reasons for the pull-ups. And since we don't know what they connect to (looking leftwards past the schematic), we can't add much yet. The rest is easy to see. The two ICs are daisy-chained together. And their control lines tied in parallel. Can you work out the details from there? \$\endgroup\$
    – jonk
    Aug 6 at 7:41
  • \$\begingroup\$ @jonk Thanks for the hints. I studies it a bit, but I can not figure out either should I read the top chip first, then read the bottom chip, or both at the same time? \$\endgroup\$
    – DEKKER
    Aug 6 at 11:10
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    \$\begingroup\$ I'm going to sleep now. If you don't have sufficient help when I find time tomorrow, I'll try to lay out what help I can then. \$\endgroup\$
    – jonk
    Aug 6 at 11:14

2 Answers 2

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Context

You get a lot with the 74HC589. You can latch the parallel input independently from what's actively going on with the shift register. And that's a nice-to-have in a part like this.

The way it's arranged, pin 12 (RCK on the schematic) of both parts are wired in parallel to the control line named BP_STRB1. A rising edge here will take a snapshot of the 16 MODx_STATUSy wires (pins 1-7 and 15) and capture it into the data latch. Since both parts are tied to this control line, the rising edge affects both of them at the same time. Obviously, that means all 16 MODx_STATUSy wires are captured, simultaneously. (You cannot capture some of them at different times from others.)

The above capture can take place at any time during the serial-shifting process for an earlier capture. That doesn't mean you have to do that. It just means you can, if you want to. This is because the data latch isn't the shift register. So you can change the data latch even when you are actively shifting out a prior value. Or, you can capture the MODx_STATUSy wires, wait a while, transfer them into the shift register and shift them out at a later time, delay still longer after that is done, and only capture the MODx_STATUSy wires when nothing else is going on. It works either way.

But a reason for selecting such a nice, full-functioned chip like this one instead of, for example, the 74HC165, is that you can load the next 16-bit word to be shifted out while a current 16-bit word is still in the middle of being shifted out. This 'double-buffering' allows the shifting process to be unbroken (continuous.) Whether or not that's desirable is another thing. But it's pretty powerful when you need it.

As you already know, I'm sure, the serial sections of these two devices are wired so that they are chained together. Pin 9 (\$Q_{_\text{H}}\$ output) of one of them ties into pin 14 (\$S_{_\text{A}}\$ input) of the other one. That causes the serial sections of the pair of ICs to become a single 16-bit shift register. As a consequence, it makes complete sense to ensure (1) that their serial shift clocks (pin 11) are tied together to the control line SPI5_SCK; (2) that their mode controls (pin 13) are tied together to the control line BP_STRB4; and (3) that their output enables (controls the tri-state condition of the \$Q_{_\text{H}}\$ output) are tied together to the control line BP_NCS1. That's because the serial shift register is being treated entirely as a single 16-bit shift register. So there's no need to separate out these lines.

One could consider the idea of using a pull-up (or pull-down) where the \$Q_{_\text{H}}\$ output of one ties to the \$S_{_\text{A}}\$ input of the other. But I guess the designer here didn't care much because the shift register won't be "in use" when SPI5_MISO is tri-stated (if it ever is.)

Questions/Answers

What are the SLOAD and RCK pins doing in this circuit?

You need a rising edge on BP_STRB1 to sample the MODx_STATUSy wires. If you don't generate it, they won't be sampled. If you don't sample them, then you can't latch their value into the shift register. And if you can't get their values into the shift register, you can't shift out the 16 bit status. So you cannot ignore BP_STRB1. You will have to actively control that line/wire.

You need to apply a LOW on BP_STRB4 long enough to ensure the 16 bits captured by the rising edge on BP_STRB1 are transferred into the shift register. Once that transfer is complete and you are ready to start shifting data, you need to apply a HIGH to enable that behavior. Obviously, you have to actively control this line, too, or else you either (1) won't be able to get the captured status into the shift register or else (2) won't be able to shift the captured status out through SPI5_MISO. (Assuming BP_NCS1 isn't tri-stating it.)

What happens if I ignore those pins? I just want to read all the 16 bits over SPI.

Per the above discussion, nothing good will happen if you ignore them. You need to operate them and in the right way. Or else you won't get what you want.

The other thing, why are there pull-ups for each input of the shift register?

I can't give you a precise answer because I don't know what's driving those wires. If the output driver is an open-collector or open-drain output, or if it can be tri-stated when the schematic you shared is being actively used to capture the wire values, or if those wires are tied to a connector that may not have anything connected to it, then the resistors are desirable (something of those or of similar values.) If the output driver is always active and there is no connector that may be left open, then perhaps they aren't needed.

They are pulled high, so if there are no drivers tied to those inputs then they will read as '1' and not '0'.

Does this mean the outputs are 1 when the input of shift register is 0?

I don't understand this question. Exactly what "outputs" do you mean? And are you suggesting that you think the resistors "invert" the values? I'm actually confused by the question. So I can't meaningfully answer it.

That's all I can add for now.

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    \$\begingroup\$ It is all clear now! Thank you very much for your time \$\endgroup\$
    – DEKKER
    Aug 7 at 20:54
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The 74HC589 consists of an 8 bit data latch and an 8 bit shift register. RCLK loads the 8 bit input into the data latch. SLOAD loads the contents of the data latch into the shift register. Once in the shift register you can clock the data out via SPI.

If you follow the above sequence, it should work as you expect.

I’d suggest you refer to the 74hc589 datasheet for more information.

Pullups? Maybe the expected input is a switch to 0V. In which case an active switch would read as a logic ‘0’

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