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I'm designing an AC-coupled low-noise preamplifier that will likely use parallel JFETs as the first amplifier stage.

One of the things I'd like to measure is the noise of very quiet regulators. JFETs are susceptible to damage from forward gate-source voltages. Additionally, to get the best noise performance out of the JFETs, I'd like to operate them at 0 gate-source bias.

Therefore, I'm designing a protection circuit to keep this voltage within safe limits (needed, for example, when the power supply is turned on or attached to the preamplifier).

My question is: what's the maximum safe gate-source voltage these JFETs can be exposed to and still ensure long-term device reliability?

Let's take the CPH3910 as an example. The datasheet specifies 10 mA gate current max. I ran a spice simulation using the manufacturer-provided device model and found the following relationship between IGS and VGS (solid line is 27C, dashed is 100C).

enter image description here

It's not really discernible in the plot, but 10 mA occurs at about 0.73 V. Since I'm basically modelling just a PN junction, and the IV curve follows an exponential, small decreases in the applied voltage produce large decreases in the current. Is limiting the gate current to around 1 μA safe?

To what extent can the JFET survive short deviations at higher gate currents? My present plan for the protection circuit is to use a comparator and load switch (MOSFET), which will, of course, have a non-zero turn-on time. I'll probably add a BAV99 after that for additional protection.

How do I assess what sort of short-term higher gate currents are safe?

FYI I'll measure the actual IV characteristic of the JFET with a curve tracer to ensure the Spice model is accurate before I construct the circuit.

Also, I expect some people will be tempted to point out that BJTs do better than JFETs in amplifying noise from a low-impedance source such as a power supply. I'll probably explore building another circuit using BJTs in the future, but for the meantime I'm sticking with JFETs. One reason for this is I'd like this to work with higher-impedance sources too and the performance of JFETs should be adequate for even the quietest regulators.

EDIT

I updated the plot to show the IV curve at 100C, since someone pointed out this relationship is highly temperature-dependent.

EDIT 2

I'm adding a plot comparing the IV characteristic of a BAV99 and CPH3910, which should be helpful in determining how much current the BAV99 steals from CPH3910.

enter image description here

And, in the following I've added a 10ohm resistor to the CPH3910 gate. Helps a bit, but maybe not enough.

enter image description here

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    \$\begingroup\$ Why don't you test a JFET by forward biasing the gate continuously at 10mA or 5mA? If it lasts for minutes or hours you know you're good. It's not like there's a gate oxide to blow so I would think you only have thermal concerns not unlike a normal diode. And 1uA is like...leakage current for diodes. \$\endgroup\$
    – DKNguyen
    Aug 6 at 18:10
  • \$\begingroup\$ @DKNguyen I'll do that. Performing a similar test for pulses of above absolute max current will be a bit trickier, however, as I don't currently have a pulse generator (though maybe this is a good excuse to get one!). Or I could build my own simple pulse generator. \$\endgroup\$
    – MattHusz
    Aug 6 at 18:25
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    \$\begingroup\$ I need an excuse to get a function generator. \$\endgroup\$
    – DKNguyen
    Aug 6 at 18:28
  • \$\begingroup\$ Are there no op-amps that would have suitably low noise in your bandwidth of interest? And, of course, what is your bandwidth of interest? \$\endgroup\$ Aug 6 at 19:15
  • \$\begingroup\$ @Kubahasn'tforgottenMonica ideally 0.1Hz - 1MHz (higher if I can manage it, but 1MHz is sufficient). Yeah, some op-amps might. I need to investigate a bit more. The AD8428 looks intriguing. Partly, doing this with JFETs is a fun design challenge, and I expect I can get lower noise with them too. \$\endgroup\$
    – MattHusz
    Aug 6 at 19:27

2 Answers 2

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JFETs have no long-term reliability problem with the gate junction being forward biased provided you limit the current. It’s a diode junction, not an insulator as in a MOSFET.

A typical datasheet limit is 10mA, so if you keep it to a few mA you will be very safe.

You could shunt most of the current away with a larger diode, but then you'd have some bias current and noise current from the diode leakage or possibly photodiode current if it's a glass diode. If the Vgs is almost zero the first two may not be important.

If you want an all-in-one option with performance guarantees, you could consider the TI (nee Burr-Brown) JFE150 which incorporates a clamp diode that is rated for 200mA for 50ms pulse, and also has reasonably low typical noise. From the datasheet (emphasis added):

When biased at 5 mA, the device yields 0.8 nV/√Hz of input-referred noise, giving ultra-low noise performance with extremely high input impedance (> 1 TΩ). The JFE150 also features integrated diodes connected to separate clamp nodes to provide protection without the addition of high leakage, nonlinear external diodes

enter image description here

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  • \$\begingroup\$ Very helpful, thank you! I added a plot comparing the IV characteristic of the CPH3910 and the BAV99 (if this were used as a protection clamp). The BAV99 has greater conduction for most bias voltages, but seems to fall short just where it matters. Any thoughts on something else that might work well here? I think shottkys are out of the question since I want MOhm impedance or greater between gate and source at very low voltages. The shottkys I looked at had resistances in the 10s of kOhms at these levels. Or, I guess I could experiment with the different gate resistor levels after the clamp. \$\endgroup\$
    – MattHusz
    Aug 6 at 21:43
  • \$\begingroup\$ Any idea about the ability of JFETs to withstand very short gate currents in excess of the rating? \$\endgroup\$
    – MattHusz
    Aug 6 at 21:44
  • \$\begingroup\$ @MattHusz tbh, I don't have solid information. I would not expect it to be a problem if the energy is limited, but I could be wrong. See my edit above on another option. \$\endgroup\$ Aug 6 at 21:57
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    \$\begingroup\$ The JFE150 looks great. Appreciate the suggestion. \$\endgroup\$
    – MattHusz
    Aug 6 at 22:25
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Put a small diode (e.g. 1N4148 or 1N914) in parallel with the FET gate-source, and a small (say 10 Ω) R to the gate. The additional noise from the 10 Ω won't be significant.

While the data sheet is correct; consider that the gate current vs. gate V curve has a very strong temperature dependence, and at higher temperatures, the specific voltage you want to limit to won't be sufficient.

If you are building a protection circuit, you'll need to ensure it turns on before the main circuit.

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    \$\begingroup\$ Any reason to use the 1N4148 (or two) over a BAV99? None of these conduct appreciably before the JFET PN junction (I think I'd need a schottky for that, but that presents too low of a shunt resistance at low voltage), but maybe with the series resistor and protection circuit it's ok. Good point about the temp. Hadn't considered that. \$\endgroup\$
    – MattHusz
    Aug 6 at 19:35
  • \$\begingroup\$ Not really; they are very similar (capacitance, leakage). \$\endgroup\$
    – jp314
    Aug 6 at 20:08
  • \$\begingroup\$ FYI I updated the original plot to show the relationship at T=100 as well. That's very conservative, as this shouldn't get particularly hot. \$\endgroup\$
    – MattHusz
    Aug 6 at 21:03

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