Estimate maximum short-duration power dissipation

Question

I'd like to estimate maximum device power dissipation over short durations given metrics commonly provided in datasheets. For example, I might ask how much power can some 1/4W resistor dissipate over a duration of 1ns, 1us, or 1ms and this method would give me a rough estimate.

I have a guess about how to perform such an estimation, but it would be great to have someone who actually understands this to confirm or correct my guess. I would also very much appreciate links to resources/literature about this if that exists.

Here's my thought process. First, I'll make the following assumptions: (1) device damage can be predicted by peak internal temperature (e.g., junction temperature in an IC), and (2) we deal with sufficiently short time frames that approximately no heat is lost to the environment. The change in temperature (\$T\$) of a device can be determined by its heat capacity (\$C\$) and the heat (\$Q\$) added to it through the equation

$$ C = \frac{dQ}{dT}. $$

\$C\$ is a function of \$T\$, hence the use of infinitesimal quantities. I'll make the simplifying assumption that \$C\$ is not a function of \$T\$. Obviously this isn't really a valid assumption, but the extent to which it produces errors in the result, I don't really know. The assumption is often made for sufficiently small changes in temperature. And, perhaps for the types of temperature changes we care about (typically 125C or less), it may still produce somewhat reasonable results. In any event, in this approximation, we can instead write

$$ C = \frac{\Delta Q}{\Delta T}. $$

Now, we need to know the maximum temperature before damage to the device results. Datasheets often provide this information. We also need to know the ambient temperature. The maximum \$\Delta T\$ is the difference between these. We also need to know \$C\$. If the datasheet provides a peak power rating and the time duration, then we can determine \$\Delta Q\$ and solve for \$C\$. Let's take as an example the JFE150. This JFET contains clamp diodes to protect against gate-source overvoltages, among other things. The datasheet specifies a maximum clamp diode current of 200 mA over a 50 ms rectangular pulse. The spice model for this device provides a diode model for the clamp diodes, which we could use to determine the forward voltage drop at 200 mA, but let's keep things simple and just assume a 0.7 V Vf. Using these numbers gives us \$\Delta Q = 7\,\text{mJ}\$, where J is energy in Joules. The datasheet does not specify the temperature at which the diode is rated for that peak current. I'll assume 25C and take the max temperature (specified in the datasheet) of 150C. This gives \$C=56\,\text{uJ/C}\$. Now imagine we want to determine the max power during a 1us pulse with the same starting temperature of 25C. That gives 7kW. The corresponding current will depend on the IV curve (temperature-dependent). This same procedure could easily be adapted to other durations and ambient temperatures.

The datasheet also provides the steady state maximum DC current as 20mA. We might use the same procedure above with a longer time duration and the max steady state current as a sort of rough sanity check. Using this procedure with a time duration of 1s gives a max current of 10mA (using the same 0.7V forward drop). We would expect the estimate to underestimate reality as our model assumed no heat loss to the environment. It's worth emphasizing that this sanity check is very rough. I could change the duration and the power estimate would change inverse proportionally. But, the fact that it produces a result in the right ballpark is maybe promising.

It's difficult for me to tell how reasonable or ridiculous this result is. 7 kW seems pretty extreme, but 1 us also isn't very long. Either way though, this method probably reaches limits where max temperature is no longer an adequate method of predicting damage. For instance, other forms of damage such as dielectric breakdown may become relevant.

Is an analysis such as this in any way useful? If not, is there an alternative method that provides more reasonable estimates? I want to emphasize that the goal here is to get something rough. More precise results would of course need to drop a lot of the above assumeptions and consider precise damage mechanisms. Another method would be to perform tests, of course.

Several other thoughts. If a peak power metric is not provided in the datasheet, then performing a similar calculation would seem quite a bit more difficult. It's possible to look up the specific heat capacity of materials like silicon, but you also need to know the mass of the sample.

Typical thermal modeling using thermal resistance doesn't seem to be useful for peak power estimates. For sufficiently short durations over which (presumably) almost no heat is lost to the surroundings the thermal resistance approaches infinity, so any power dissipation drastically increases the device temperature. That can't be right.

Answer 1

Your calculations are OK in principle. In practice, the detailed construction of most types of components makes it difficult to identify the relevant heat capacities at the different timescales correctly.

Take for example the construction of two types of resistor. One is metal film on ceramic, the other is wire-wound. In the first, the mass of the resistive element is a tiny fraction of the total mass of the device. With a 1 us pulse, only the metal film gets hots, there is little heat transfer to the substrate. With a 1s pulse, the entire resistor body is available to absorb heat, and the effective heat capacity is orders of magnitude higher. With a 10s pulse, the area of PCB around the resistor absorbs heat. Any longer length pulse, we are approaching the continuous power dissipation limit.

With a wire-wound resistor, the mass of the resistive element will be a much larger fraction of the resistor weight, giving a much higher usable heat capacity. Whether the pulse is 1 us or 1 s long, heat is absorbed uniformly throughout the wire. Wire-wound resistors are often given a pulse power specification in the data sheet.

Semiconductors are often supplied with a SOA (Safe Operating Area) graph in the data sheet, which gives the maximum voltage and current at various pulse lengths that the device can withstand. This encompasses all the considerations of how fast heat spreads from the active areas to the support and heat-sinking areas, temperature balance between parts, the different time constants of bond wires etc etc.

Here is an example SOA graph from an Analog Devices technical article for use of MOSFETs ...

As you can see, while it's generally the shorter the pulse, the more power the device can take, the detail is very complicated.

Answer 2

Your calculations are correct in principle, but the real world effects are different for semiconductors and lumped devices such as resistors.

In a resistor, power is generally distributed quite uniformly across the bulk of the device.

In addition, the material likely has negligible temperature coefficient of resistance. This means that as it heats up, there is no significant 'crowding' of the power dissipation (if the resistance of a portion increased, and you forced a constant current, then that portion would heat up, increase resistance, increase localized power, heat up, ...). Therefore the applied power will tend to heat up the structure reasonably uniformly and you can apply your calculations.

In a semiconductor, there are more complex effects in play. Assuming your applied voltage doesn't immediately cause an oxide breakdown (can occur in ns, and is non-recoverable), effects such as conductivity modulation, and the negative temperature coefficient of a pn junction forward voltage may mean that the current 'crowds' -- i.e. doesn't flow uniformly across an area. For instance in a power FET (LDMOS), once (even a small portion) of the device reaches junction temperatures of 300-400 C, there is a parasitic NPN (which forms part of the drain-source body diode) which reaches a turn-on voltage of nearly zero. This causes this portion to conduct disproportionally more, heat up more, and .... The precise limits depend on the thermal conductivity of the structure. On a large scale, this is the reason for "thermal runaway" in not-correctly connected paralleled MOSFETs.

This effect also tends to occur in BJTs, and is characterized commonly as "second breakdown" -- a short-term power limitation.

A Zener diode (with a BV > 5 V) tends to have a positive tempo, so localized heating will turn that section off, and tends to distribute more evenly.

However, at high internal temperatures (say >> 300 C), the commonly used Aluminum metallization on ICs will be driven into the silicon structure by heat and electromigration effects and will generally cause a failure. Some devices can be failed by ESD pulses only 1 ns duration.