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This is a VHDL question.

I have a temperature sensor that sends out serial data. I have converted the serial data into 16-bit parallel data. I then copy that data into a different 16-bit register.

I have to be able to compare a known value with what is in the that 16-bit register and then export known data from a different register to my 8-bit data output.

My problem is that I have tried everything I can think of but to no avail.

I would really appreciate someone advice and help on this one.

I have the sample code and the debug simulation.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity T_Sense is
port(
     nRST   : in std_logic;
     SYSCLK : in std_logic;
     B_PWR  : in std_logic;

     T_SO  : in std_logic;
     T_SCK : out std_logic;
     T_nCS : out std_logic;

     L_DAT : out std_logic_vector(7 downto 0)
     );
end entity;

architecture RTL_T_Sense of T_Sense is

    signal TClk   : integer := 1;
    signal clkTmp : std_logic;
    signal TS_CLK : std_logic;
    signal TnCS : std_logic;

    signal HoldReg : std_logic_vector(15 downto 0);
    signal TSReg   : std_logic_vector(15 downto 0);
    signal LDatReg : std_logic_vector(7 downto 0);

    type LCDOUT is (BPWR, CS_EN, TDAT1, CSDIS);
    signal NXT_T : LCDOUT;

BEGIN

---- 4MHz Temperature Sense Clock
TEMPERATURE_CLK_PROC : process(nRST, SYSCLK)
begin
    if (nrsT = '0') then
        TClk <= 1;
        clkTmp <= '0';
    elsif rising_edge(SYSCLK) then
        TClk <= TClk + 1;
            if (TClk = 2) then
                clkTmp <= NOT clkTmp;
                TClk <= 1;
            end if;
    end if;
end process;
TS_CLK <= clkTmp;

---- Temperature Sensor Data In
DATIN_PROC : process(nRST, TS_CLK)
Begin
    if (nRST = '0') then
        HoldReg <= (others => '0');
    elsif rising_edge(TS_CLK) then
        HoldReg <= HoldReg(15 downto 1) & T_SO;
    end if;
end process;
    TSReg <= HoldReg;

---- Temperature Sensor Data Compare
TSDC_PROC : process(nRST, TS_CLK)
Begin
    if (nRST = '0') then
        TnCS <= '1';
    elsif rising_edge(TS_CLK) then
        case NXT_T is
            when BPWR =>
                if (B_PWR = '1') then
                    NXT_T <= CS_EN;
                else
                    NXT_T <= BPWR;
                end if;

            when CS_EN =>
                TnCS <= '0';
                NXT_T <= TDAT1;

            when TDAT1 =>
                if TSReg(15 downto 0) = X"7D00" then
                    LDatReg <= X"31";
                end if;

            when CSDIS =>
                TnCS <= '1';

            when others =>
                NXT_T <= BPWR;

        end case;
    end if;
end process;

    T_nCS <= TnCS;
    T_SCK <= TS_CLK;

END RTL_T_Sense;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity TB_T_Sense is
end entity TB_T_Sense;

architecture T_Sense_TB of TB_T_Sense is

    signal nRST   : std_logic := '0';
    signal SYSCLK : std_logic := '0';
    signal B_PWR  : std_logic := '0';
    signal T_SO   : std_logic;
    signal T_SCK  : std_logic;
    signal T_nCS  : std_logic;
    signal L_DAT  : std_logic_vector(7 downto 0);

    signal clkprd : TIME := 50 ns;

    signal Tprd   : TIME := 200 ns;
    signal TCLK   : std_logic := '0';

    signal tmpReg : std_logic_vector(15 downto 0);
    signal tmpDat : std_logic_vector(15 downto 0) := X"7D00"; ``

component T_Sense
port(
     nRST   : in std_logic;
     SYSCLK : in std_logic;
     B_PWR  : in std_logic;

     T_SO  : in std_logic;
     T_SCK : out std_logic;
     T_nCS : out std_logic;

     L_DAT : out std_logic_vector(7 downto 0)
     );
end component;

BEGIN

UUT_T_Sense : T_Sense
port map(
         nRST   => nRST,
         SYSCLK => SYSCLK,
         B_PWR  => B_PWR,
         T_SO   => T_SO,
         T_SCK  => T_SCK,
         T_nCS  => T_nCS,
         L_DAT  => L_DAT
         );

    nRST <= '1' after 75 ns;
    SYSCLK <= NOT SYSCLK after clkprd/2;
    B_PWR <= '1' after 25 ns;
    TCLK <= NOT TCLK after Tprd/2;

PISO_PROC : process(nRST, TCLK)
    variable bitCnt : integer range 0 to 7;
    variable oneShot : std_logic;
Begin
    if (nRST = '0') then
        tmpReg <= (others => '0');
        bitCnt := 0;
        oneShot := '0';
    elsif rising_edge(TCLK) then
        if (oneshot = '0') then
            tmpReg <= tmpDat;
            bitcnt := 0;
            oneshot := '1';
        elsif (bitcnt /= 7) then
            tmpReg(15 downto 1) <= tmpReg(14 downto 0);
            bitcnt := bitcnt + 1;
        else
            bitcnt := 0;
        end if;
    end if;

end process;

    T_SO <= tmpReg(15);

END architecture T_Sense_TB;

T_Sense Debug and Simulation

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1 Answer 1

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One problem pops out right away -- the following line is NOT a shift register:

  HoldReg <= HoldReg(15 downto 1) & T_SO;

You probably intended something more like:

  HoldReg <= HoldReg(14 downto 0) & T_SO;

There are many other problems with your state machine:

  • NXT_T is never properly initialized (although your simulation seems to deal with it somehow).
  • There's no way to leave the TDAT1 state.
  • There's no way to leave the CDIS state.
  • It isn't at all clear how you know when 16 bits have accumulated.
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