2
\$\begingroup\$

I have LVDS SerDes signals coming out from FPGA1 IO and have a few questions regarding the design.

My plan is to output the signals from the FPGA1 to a connector and from the connector a cable will be used to connect FPGA1 to FPGA2. The LVDS SerDes is 1 GHz and the cable to be used is a shielded, twisted pair cable.

  1. Do I need to use a driver before outputting the signals to the connector?

  2. If a driver is not used and the FPGA output drive current it 4 mA, what would be the maximum length supported at the given frequency? How is that calculated?

  3. Any recommended driver that is easy to use in this case?

\$\endgroup\$
2
  • \$\begingroup\$ LVDS is an electrical specification. Does the FPGA output a GPIO signal or an LVDS signal? \$\endgroup\$
    – CL.
    Commented Aug 8, 2022 at 15:55
  • 1
    \$\begingroup\$ IO standard is set as LVDS \$\endgroup\$
    – Shannon
    Commented Aug 8, 2022 at 17:01

2 Answers 2

2
\$\begingroup\$

LVDS outputs from FPGAs are fully capable outputs that will drive the same as an external driver. The distance will be determined by the characteristics of the cable the same as with external drivers.

However, I have often used external LVDS drivers for one of two reasons:

  1. FPGA pin shortage - LVDS uses two pins instead of one and may require the I/O bank has to be set to a specific voltage that is not compatible with other GPIOs.

  2. If the LVDS signals are required to go to an external connector that could be subject to accidental ESD abuse it may be better to use an external driver to take the brunt of any damage rather than the expensive FPGA (some FPGAs I have used have cost up to $30,000).

\$\endgroup\$
2
  • \$\begingroup\$ Assuming the cable is good, what would be the way to calculate the maximum length given the drive strength of the IOs? \$\endgroup\$
    – Shannon
    Commented Aug 8, 2022 at 17:06
  • 1
    \$\begingroup\$ @Shannon, the maximum length depends on the cable attenuation and the receiver sensitivity just as much as on the transmitter drive strength. Also on any interference sources in the environment. \$\endgroup\$
    – The Photon
    Commented Aug 8, 2022 at 17:59
1
\$\begingroup\$

The LVDS interfaces in FPGAs are just as capable for communications as dedicated LVDS I/O driver and receiver ICs.

However, external LVDS circuits can provide significantly increased electrical protection and ruggedness over the FPGA LVDS pin I/O.

This protection circuitry might be one/more of:

  • LVDS to single-ended I/O driver/receiver ICs, with stronger protection
  • Clamp/Zener diodes for overdrive voltages
  • TVS diodes for infrequent transients like ESD

This protection can be valuable for off-board connections, for example going up cables prone to electrical interference, ESD or nasty voltage injection.

This is true of any interface signals that connect an FPGA to something, could just as well be serial LVTTL, ADC, serdes etc.

What protection is needed comes from the system reliability and cost requirements:

  • Reliability. Can a failure to protect LVDS be allowed to stop the FPGA working correctly? That depends on what else the FPGA does and controls. On an Xmas tree lights controller: yes. On an aircraft EMS: no.

  • Cost. What is the overall cost (parts, rework, service installation or just board scrapped) of an FPGA failure. A £3 FPGA failure with total board replacement cost of £250 with 1-in-10 incident rate makes £5 of protection circuitry very worthwhile.

So, like all interface circuitry, it's something to assess at a board/system level.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.