I'm a software engineer, not really experienced in the hardware design, looking to confirm if I correctly designing the following piece:

I have a FOC motor controller chip (TMC4671) that is only able to provide 2-line PWM signal to the gate driver (PWM_HIGH that goes logic high to enable high side of the MOSFET half-bridge, and PWM_LOW that goes high to enable the low side. Both signals LOW means both sides of half-bridge are off, and it's not supposed to have a state where both signals are HIGH). To simplify my schematic, I would prefer to use the "Power Stage" IC (e.g. TI CSD97395Q4M) that only has one tri-state PWM line to control it (HIGH signal means high-side on, LOW signal means low-side on, high-Z means both sides off).

I believe the following schematic (2-input NOR gate + Tri-state digital buffer with inverting ENABLE input) would work to convert signals between these 2 ICs: schematic

Apart from making the bandwidths/timings and voltages match, is there anything I missed here? Is it supposed to work at all?


  • \$\begingroup\$ Just a note that if actually building this, tie any unused inputs to a power/ground rail and add decoupling capacitors at each chip. \$\endgroup\$
    – rdtsc
    Aug 10, 2022 at 13:46

1 Answer 1


From your description of the problem, the OR and tri-state buffer circuit you show is fine.

It suits the PWM input pin function described in the CSD97395Q4M datasheet.


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