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Assume that within an FPGA, I have two data streams that are being driven by two clocks. The two clocks are generated by 2 physically separated PLLs (still within the same FPGA), both of which have the same single input reference oscillator, and both PLLs are setup identically in terms of parameters.

I now want to combine both streams of data and feed to a single logic block with a single clock. Assume after the PLLs are locked, do I need to perform a clock crossing operation, or since both PLLs are the same within some tolerance, Can I just grab one of the clocks and use all signals directly?

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    \$\begingroup\$ PLLs have jitter (well, all clock distribution schemes have jitter, but some more than others). Does the jitter tolerance allow you to combine the streams without violating the receiver's setup and hold requirements? If yes, then yes, just grab one clock. If no, then you need to do something else. Change your design to increase jitter tolerance, or implement clock domain crossing circuits. \$\endgroup\$
    – Neil_UK
    Commented Aug 11, 2022 at 18:57
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    \$\begingroup\$ I had to do something like that recently -- I needed to combine the outputs of four high-speed serial-output ADC chips into a single stream of words. Each ADC was given the same reference clock, but the data came back with its own clock with a fairly arbitrary phase relationship. I was able to determine that after deserialization, the total variation in phase at the word clock rate was small enough that a simple register sufficed to align the four channels. You will have to do a similar analysis for your situation. Setting up the timing constraints correctly becomes rather "interesting". \$\endgroup\$
    – Dave Tweed
    Commented Aug 11, 2022 at 19:34
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    \$\begingroup\$ ... Why not clock both data stream generators with the same PLL? \$\endgroup\$
    – user20574
    Commented Aug 11, 2022 at 23:08
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    \$\begingroup\$ Why can't you ? \$\endgroup\$
    – user20574
    Commented Aug 15, 2022 at 19:36
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    \$\begingroup\$ Technically, they are two asynchronous clock domains even if the frequencies / phase shift are same. Because, they can have jitter variations which are independent to each other. But as Neil said, if jitters are tolerable to meet setup/hold (especially if larger frequencies), you can analyse this path using STA or manually and take a decision to use one of the clocks or put an Async FIFO. But I wonder why you need two clocks at all for your requirement? \$\endgroup\$
    – Mitu Raj
    Commented Aug 17, 2022 at 9:45

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Yes, you do, because the two PLLs may not be perfectly phase-aligned and the relative phase alignment could change. The misalignment could lead to a hold time violation.

In this particular case, if you do not use a clock crossing circuit to cross clock domains, your design will probably appear to work in practice, but would have a latent bug which would be very difficult to discover through testing.

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