I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"
It says that with AND-Latch based ICG there could be a missing pulse at the output if there is a glitch during rising transition of input clock (clk)
Why does this issue make it less reliable when driving negative edge triggered FF ? If there is a missing pulse, it would be expected that the result would arrive one cycle later. Is the reliability related to wrong result ?