I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"


It says that with AND-Latch based ICG there could be a missing pulse at the output if there is a glitch during rising transition of input clock (clk)

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Why does this issue make it less reliable when driving negative edge triggered FF ? If there is a missing pulse, it would be expected that the result would arrive one cycle later. Is the reliability related to wrong result ?

  • 2
    \$\begingroup\$ Honestly, this look like a research work that's just there for the sake of research. Latch based IGC is universally accepted solution for gating at all nodes. And enable doesn't glitch like that so close to clock edge because it typically comes from a synchronous logic in the same clock domain and this path is timing proven for setup and hold. IGCs are designed as hard IPs with stringent timings to make it work given setup & hold are met. \$\endgroup\$
    – Mitu Raj
    Aug 12, 2022 at 13:02
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    \$\begingroup\$ If at all enable glitch happens close to clock edge like that due to noise or so, metastability occurs, but that's true for any synchronous element. That's why we do STA, noise /crosstalk analysis of designs, add CDC structures etc. \$\endgroup\$
    – Mitu Raj
    Aug 12, 2022 at 13:03


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