2
\$\begingroup\$

I have to interface a fast ADC with an FPGA and then do the data processing. The FPGA used will be Zynq Ultrascale+ RFSoC ZU29DR. I have been given the information that ADC_clk = 4x FPGA_clk. ADC output data is 12/16-bits. The data processing will be multiply-accumulate over a number of samples.

I = I + adc_data * cos;

Q = Q + adc_data * sin;

There is a data sample output at every clock of ADC. So, it will be something like:

I[0] = I[0] + adc_data[0] * cos[0];

Q[0] = Q[0] + adc_data[0] * sin[0];

I[1] = I[1] + adc_data[1] * cos[1];

Q[1] = Q[1] + adc_data[1] * sin[1];

And so on.

I have a DDS CORDIC-LUT module that can be instantiated to generate 4 sin, cos values parallelly based on the phase word. What I'm not sure about is how to multiply with adc_data as adc generates faster than what the FPGA can accept.

I have come up with the below timing diagram and architecture. Any input will be appreciated.

enter image description here

enter image description here

\$\endgroup\$

0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.