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I have to interface a fast ADC with an FPGA and then do the data processing. The FPGA used will be Zynq Ultrascale+ RFSoC ZU29DR. I have been given the information that ADC_clk = 4x FPGA_clk. ADC output data is 12/16-bits. The data processing will be multiply-accumulate over a number of samples.

I = I + adc_data * cos;

Q = Q + adc_data * sin;

There is a data sample output at every clock of ADC. So, it will be something like:

I[0] = I[0] + adc_data[0] * cos[0];

Q[0] = Q[0] + adc_data[0] * sin[0];

I[1] = I[1] + adc_data[1] * cos[1];

Q[1] = Q[1] + adc_data[1] * sin[1];

And so on.

I have a DDS CORDIC-LUT module that can be instantiated to generate 4 sin, cos values parallelly based on the phase word. What I'm not sure about is how to multiply with adc_data as adc generates faster than what the FPGA can accept.

I have come up with the below timing diagram and architecture. Any input will be appreciated.

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1 Answer 1

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The FPGA should have transceivers that work with clocks much higher than the FPGA clock. These transceivers widen the data word and turn a "narrow word, high clock" into "wide word, slow clock". You may need an external SERDES chip to package up the ADC data into one or more "gigabit" narrow (serial-ish) streams that the FPGA will then internally deserialize/widen.

Generally, you need to interface the ADC so that the FPGA fabric sees the data as a 64-bit word at the FPGA clock (or a 128-bit word at 1/2 FPGA clock, etc.).

The widening could be done externally, in a pinch, using discrete D-registers, timed from a programmable clock delay and divider chip. The clock gen would make 4 clocks at the fADC/4 frequency, and their phases would be adjusted so that the registers would properly capture each 4th word from the ADC, with a 1/fADC offset in phases between the registers.

External widening consume a lot of I/O and would be a pain to lay out. Counterintuitively perhaps, serializing into a faster data stream right next to the ADC will be easier, as there'll be fewer differential traces to lay out between the SERDES and the FPGA.

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