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In solving the differential pair with an active load, I am able to find the gain without including R1 as shown in the figure. When R1 is included, I am stuck on how to proceed. Could you help me out?

This was a question from razavi textbook. I thought of drawing the small signal model and then analyze it. But this became cumbersome. Then I checked through the solution in which he has divided the inputs into differential and common mode. I understood that the common mode gain is zero. For differential gain, he considered one input at a time vd/2 and -vd/2. Also assumed the source of M1 and M2 to be small signal ground. This is where I was confused. How can it be a small signal ground?

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PS: Solution: enter image description here

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    \$\begingroup\$ Notice that we are dealing here with a small-signal approximation. Why is the voltage at the source is fixed? This voltage remains fixed due to the fact that we are again dealing with a symmetrical AC input signal. This means that if Vin1 rises by a small amount Vin2 will drop by the same amount. For example, if Vin1 increases the Is1 will increase too let's say from 1mA to 1.2mA (Iss = 2mA) and Is2 will decrease by the same amount from 1mA to 0.8mA. This means that Iss current has no AC component ΔIs1+ΔIs2=0A (what a surprise). Hence the voltage at the source remains fixed thus, AC GND. \$\endgroup\$
    – G36
    Sep 11 at 16:01
  • \$\begingroup\$ @G36 It can be AC ground only if the circuit is symmetrical. AC component of current is zero which is obvious. But how can we say that it is AC ground? \$\endgroup\$
    – prashanth
    Sep 12 at 4:01
  • \$\begingroup\$ Are you asking for circuit A or B? And what is the expected gain(s), since you have the answer? \$\endgroup\$
    – pat
    Sep 12 at 5:13
  • \$\begingroup\$ @pat I have added the solution for reference. Thanks \$\endgroup\$
    – prashanth
    Sep 12 at 6:15

3 Answers 3

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Your question about why the tail node is a small signal ground is equally valid for the simple amplifier with a current mirror load. Because that circuit is also not fully symmetrical to be split into two differential halves. I intend to answer, in which case the assumption for the small signal ground is valid for a standard amplifier, shown below with its small signal model. You can then extend the mathematics for this particular case that you are interested in, in the same manner.

schematic

simulate this circuit – Schematic created using CircuitLab

I would like to find the differential gain of a current mirror-loaded amplifier assuming the transistors are perfectly matched but without any assumptions about the tail node voltage. Since there are two independent voltages applied simultaneously to the circuit, it makes sense to use the superposition principle to find the small signal node voltages and gain. Turning the right source off and writing KCL equations for the nodes, you can derive the following:
At \$v_1\$, $$ g_{mp}v_1+\frac{v_1-v_p}{r_{on}} + g_{mn}(v_i - v_p) = 0 $$ At \$v_p\$, $$ \frac{v_p-v_1}{r_{on}} + \frac{v_p-v_o}{r_{on}} = g_{mn}(v_i - v_p) - g_{mn}v_p $$ At \$v_o\$, $$ \frac{v_o}{r_{op}} + \frac{v_o-v_p}{r_{on}} - g_{mn}v_p = -g_{mp}v_1 $$ Similarly, by turning the left source off, we can get such equations (which I do not want to type again). After some tedious algebra, we can derive the expression for the tail voltage and the output voltage (assuming I made no calculation error). $$ v_p = -\frac{g_{mn}r_{on}(1-2g_{mp}r_{op})v_i}{2g_{mn}g_{mp}r_{on}(r_{on}+r_{op})+g_{mn}r_{on}+2g_{mp}(r_{on}+r_{op})+1}\\ v_o = \frac{4g_{mn}g_{mp}r_{on}r_{op}v_i}{2g_{mp}(r_{on}+r_{op})+1} $$ After certain simplifying assumptions, that \$g_mr_o >> 1\$, these expressions can be simplified as: $$ v_p = \frac{r_{op}}{2(r_{on}+r_{op})}2v_i\\ v_o = \frac{g_{mn}r_{op}r_{on}}{r_{on}+r_{op}}2v_i $$ The second expression gives us the gain expression we already know. The first expression gives us the tail voltage. And it can be seen that if \$r_{on}\$ is very large, then the voltage at the tail remains close to 0V in AC. Do you think it makes sense?
You can think like this. Let's assume the transistors are ideal with infinite output impedance, then the load has no impact on the currents through n-MOS and antisymmetric input voltages will generate perfectly antisymmetric currents, making the tail node a virtual ground.
BTW the question in Razavi also assumes very high \$R_1\$, which means the virtual ground assumption can be made if the implicit assumption that the n-MOS have very high output impedance is valid.
I urge you to verify this with simulations.

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  • \$\begingroup\$ When we assume it aa virtual ground, we get tha gain gm(r_n//r_p) right? But it's double in ur calculations. Am I wrong somewhere? \$\endgroup\$
    – prashanth
    Sep 15 at 15:06
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    \$\begingroup\$ No, it is not double. I assumed input voltage \$\pm\Delta V\$ while you assumed \$\pm\Delta V/2\$. Thus in my expressions, you need to divide by \$2\Delta V\$ (total differential swing) or \$2v_i\$ as I have indicated in my equation, then you get the same gain. \$\endgroup\$
    – sarthak
    Sep 15 at 15:32
  • \$\begingroup\$ Please elaborate on why did you omit, in your small-signal circuit, the output resistance \$r_{O3}\$ for a diode connected MOSFET (M3)? \$\endgroup\$
    – V.V.T
    Sep 17 at 9:50
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    \$\begingroup\$ I've posted my answer with the equations that include the rO3 contribution and the resulting output voltage \$V_{out}\$ (sorry for breaking convention of using small letters for small-signal voltages, I'm using the OP variable names). Other than that, your formula for \$v_p\$ does not predict a zero AC voltage at P when \$r_{op}\$ is infinite, whereas this assumption makes the circuit symmetric. \$\endgroup\$
    – V.V.T
    Sep 17 at 10:32
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    \$\begingroup\$ Verified and discovered that \$r_{O3}\$ contribution changes \$V_{out}, \, V_P\$ values only marginally. Just followed Razavi who often uses \$1/g||r_O\$ for small signal resistance of diode connected MOSFET. Never paid attention whether it really matters. Thanks for hint. \$\endgroup\$
    – V.V.T
    Sep 18 at 13:54
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Also assumed the source of M1 and M2 to be small signal ground. This is where I was confused. How can it be a small signal ground?

Viewing these slides, it can be shown that for small signal differential analysis, the \$I_{ss}\$ node can be considered a 'virtual' AC ground (slide 24). Note that the same analysis for Bipolar is extended to CMOS (slide 54). There is also a proof and derivation of this assumption (see slide 31).

In solving the differential pair with an active load, I am able to find the gain without including R1 as shown in the figure. When R1 is included, I am stuck on how to proceed.

You have the answer in front of you, so I can only try to explain it from my intuitive viewpoint if it helps.

  1. You know that the differential gain is \$\frac{vout_{diff}}{vin_{diff}}\$
  2. Using superposition, you can find the gain for both sides or half circuits and just add them.
  3. Small signal analysis is something you have to get experience over time, unfortunately. However, from experience I can generally look at most any amplifier with a load and reduce the gain to \${gm_{in}}{Rout}\$
  4. Looking at the half circuit on the left. I can see the total Rout at drain node, is the resistance of the load device (M3) in parallel with the output resistance of M1 in parallel with R. Or, \$\frac{1}{gm_3}\$ in parallel with R (which can be assumed much larger than device output resistance in this config). Let's just call the total \$Rout_1 = \frac{1}{gm_3} // {ro}\$ Longer version of ro (including both R and \${ron_1}\$) is in your answer attachment.

Then the voltage out at that node is \$vout_1 = {I_{out_1}}{R_{out_1}} = {gm_1}{R_{out_1}}{vin_1}\$

This voltage is converted to a current by transconductance of M4 and mirrored to other output side. Or, \$Iout_2 = {gm_4}{vout_1}\$ and \$vout2 = {Iout_2}{Rout_2}\$.

Thus substituting above results for the left leg of the superposition, \$\frac{vout2}{vin1} = {gm_4}{gm_1}{R_{out_1}}{Rout_2}\$ Although subscripts and arrangement might be slightly different, this result is in agreement of result 1 of your answer.

That's the harder part, because of the additional R of leg 1.

  1. With the right leg, you just assume same \$gm_n\$ and \$gm_p\$ for both sides. You know again, general gain is \${gm}{Rout}\$ This result is much simpler.

  2. Now just add the two gains (by superposition). \${gm_4}{gm_1}{R_{out_1}}{Rout_2} + {gm_2}{Rout_2}\$ The factor of 1/2 in front, is due to the fact that each side is sourced by \$+/-\frac{vin}{2}\$

This result is equivalent to Gain result 2) in your answer. You should be able to easily convert and massage the subscripts and total output resistance of the first leg to match exactly.

Same rational can be applied to other similar types of problems.


*edit. I'll add one other analysis directly related to a FET diff pair that is used by various authors, since the other slides are not convincing given comments.

Let P be source node of FETs. If you use KCL at node P, you have \$gm1(v1-Vp) + gm2(v2 - Vp) + \frac{(Vx-Vp)}{rx} + \frac{(Vy-Vp)}{ry} =0\$

Nodes \$x\$ and \$y\$ are the drain nodes of left and right branches. Assume \$rx\$ and \$ry\$ between drain nodes and P are asymmetrical (as in this problem). The idea is that even though they are asymmetrical, if they are large enough to make the second terms insignificant, vs the first two (regardless of the asymmetry), this leaves only the first two terms. Given that gms and input devices are equivalent and vins are equivalent, but opposite sign. One can show that Vp is 0 (This second form is the exact argument Razavi uses in his text).

The same approach can be used with KCL at the drain nodes, with similar assumptions on load resistances.

Now, I've seen others argue these points as well. My only perspective (especially if you are starting to learn this) is that if the majority of experts have accepted and taught this for years as well as designers without backlash, I would just accept it for now so that you can solve for the analysis. Even without the extra R, the most used and basic single ended differential pair is asymmetrical as well (Allen & Holberg, which is like the bible of CMOS design put this in a footnote, and just admit they ignore it for clarity of teaching the concepts).

It's like GBW as being pushed (similarly in literature) as constant for years for amplifiers, but being invalid for smaller gains. This is since simplified assumptions make the concepts easier and avoid drowning students in more detailed derivations and proofs.

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  • \$\begingroup\$ This voltage is converted to a current by transconductance of M4 and mirrored to other output side. Or, \$Iout_2=gm_4vout_1\$ and \$vout_2=Iout_2Rout_2\$. : And what about the contribution of M4 output resistance into the current \$Iout_2\$? Should not we write M4 drain current as \$Iout_2=gm_4vout_1+vout_1/rO_4\$? \$\endgroup\$
    – V.V.T
    Sep 13 at 1:06
  • \$\begingroup\$ Yes I agree with this. The actual textbook solution he gave simplified it to just Rout of the right hand side -- I didn't want to distract with more details. My intention was to simplify it further for the intuition. \$\endgroup\$
    – pat
    Sep 13 at 2:29
  • \$\begingroup\$ To verify your intuition, you can run simulation. Not only with small-signal dependent VCCS's and output resistors, but also with actual models of real transistors. Feed a sine signal to the inputs and run a transient simulation. With an ideal biasing current source (Iss in my circuit, Iee in yours), you will always measure a sine wave of approx. half input signal amplitude at the node P. \$\endgroup\$
    – V.V.T
    Sep 13 at 7:04
  • \$\begingroup\$ This is one of the reason the six-transistor design of diff pair was developed: to make the active load symmetric in order to suppress this wave at P. Maybe you should verify if the lecture slide of your reference use symmetric loads for M1/M2. \$\endgroup\$
    – V.V.T
    Sep 13 at 7:05
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    \$\begingroup\$ Added a little bit to answer (more FET specific). \$\endgroup\$
    – pat
    Sep 14 at 19:24
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First start with a very great value of \$R1\$ to verify if the node P is a small signal ground. If P is a virtual small-signal ground for any R1, this should hold also for \$R1 = ∞\$, i.e., when M1/M2 drains are not connected with any resistor at all:

diffpair.png

For a DM input signal, write down KCL equations for calculating the voltages (w.r.t. the ground) at the circuit nodes: \$V_1\$ is a small signal voltage at the M1/M3 drain node, \$V_P\$ is a small signal voltage at the node P (for Pair, the connected sources of M1 & M2 diff pair transistors), \$V_{out}\$ is a small signal voltage at the M2/M4 drain node. In the absence of the bridge resistor R1, the drain currents of transistors M2, M3 and M4 are all equal to the current of the diode connected M1 (be careful when selecting current directions! I've accepted the positive currents to run counterclockwise in the closed loop of the AC current V1 -> P -> Vout -> Vdd.)

$$ (g_{m3}+1/r_{O3})(-V_1) = g_{m1}(V_{in}-V_P) + {\frac {V_1 - V_P} {r_{O1}}} \tag 1 $$ $$ (g_{m3}+1/r_{O3})(-V_1) = -g_{m2}(-V_{in}-V_P) + {\frac {V_P - V_{out}} {r_{O2}}} \tag 2 $$ $$ (g_{m3}+1/r_{O3})(-V_1) = -g_{m4}(-V_1) + {\frac {V_{out}} {r_{O4}}} \tag 3 $$ where the symbols \$g_{m1}=g_{m2}=g_m, r_{O1}=r_{O2}=r_O\$ are the identical transconductances and output resistances of NMOS transistors M1, M2; \$g_{m3}=g_{m4}=g_{pmos}, r_{O3}=r_{O4}=r_{pmos}\$ are the identical transconductances and output resistances of PMOS transistors M3, M4.

For the small signal analysis, you can substitute a resistor \$r_d = r_{O3}||(1/g_{m3})\$ for the diode connected M3, without changes in the eqs. 1-3:

small-signal-circuit

but you cannot omit the contribution of \$r_{O3}\$, when doing calculations with finite output resistances of PMOS. If you're omitting \$1/r_{O3}\$, you should also omit \$1/r_{O4}\$, because technologically these transistors are usually made identical.

After doing not-excessively-cumbersome calculations you obtain $$ V_{out} = {\frac {(2g_{pmos}r_{pmos}+1) g_m r_O r_{pmos}} {(g_{pmos}r_{pmos} + 1) (r_O + r_{pmos})}}V_{in} $$ In the process you also obtain \$V_P\$: $$ V_P = {\frac {(g_m r_O) (g_{pmos} r_{pmos})} {(g_m r_O + 1)(g_{pmos}r_{pmos}+1))}}{\frac {r_{pmos}} {(r_O + r_{pmos})}}V_{in} $$

The first fraction in this expression is symmetric w.r.t. parameters of NMOS and PMOS transistors and asymptotically tends to unity as \$g_{pmos} r_{pmos}, \, g_m r_O\$ products grow, but the fraction \$ r_{pmos}/(r_O + r_{pmos})\$ favorizes \$r_O\$ over \$r_{pmos}\$ from the point of view of ability to zero \$V_P\$ with high output resistance. With finite \$r_O\$'s, \$V_P\$ never becomes "small signal ground", however great \$r_{pmos}\$ values you select.

But notice that, for \$V_P\$ to become "small signal ground", you should secure a finite output resistance of the PMOS transistors of the active load. The NMOS output resistance \$r_O\$ should become much greater then the PMOS output resistance \$r_{pmos}\$ of the load, \$r_O >> r_{pmos}\$, which agrees with the formulas, but inconsistent with the explanation given in the accepted answer. Another way to adjust the \$V_P\$ behavior is to consider the tail current's AC component, i.e., the finite output resistance of the \$I_{SS}\$ current source.

Removing both \$r_{O3}, \, r_{O4}\$ from the small signal model, you've got two ideal current sources connected in series, which is formally unacceptable. Notice that inserting the resistor R1 as in your fig. (b) does not help with current sources connected in series. The resistor R1 connected as in fig. (a) shunts M1, but not M2. High output resistance of active load transistors decreases the driving strength and increases the pair-matching sensitivity and stiffness of the diff pair, but also increases the voltage gain. High voltage gain is favorable for the opamp input stage.

The node P voltage becomes relatively input-insensitive with the sophisticated active load called the Lee load. This design has much better CMRR.

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