First start with a very great value of \$R1\$ to verify if the node P is a small signal ground. If P is a virtual small-signal ground for any R1, this should hold also for \$R1 = ∞\$, i.e., when M1/M2 drains are not connected with any resistor at all:
For a DM input signal, write down KCL equations for calculating the voltages (w.r.t. the ground) at the circuit nodes: \$V_1\$ is a small signal voltage at the M1/M3 drain node, \$V_P\$ is a small signal voltage at the node P (for Pair, the connected sources of M1 & M2 diff pair transistors), \$V_{out}\$ is a small signal voltage at the M2/M4 drain node. In the absence of the bridge resistor R1, the drain currents of transistors M2, M3 and M4 are all equal to the current of the diode connected M1 (be careful when selecting current directions! I've accepted the positive currents to run counterclockwise in the closed loop of the AC current V1 -> P -> Vout -> Vdd.)
$$
(g_{m3}+1/r_{O3})(-V_1) = g_{m1}(V_{in}-V_P) + {\frac {V_1 - V_P} {r_{O1}}} \tag 1
$$
$$
(g_{m3}+1/r_{O3})(-V_1) = -g_{m2}(-V_{in}-V_P) + {\frac {V_P - V_{out}} {r_{O2}}} \tag 2
$$
$$
(g_{m3}+1/r_{O3})(-V_1) = -g_{m4}(-V_1) + {\frac {V_{out}} {r_{O4}}} \tag 3
$$
where the symbols \$g_{m1}=g_{m2}=g_m, r_{O1}=r_{O2}=r_O\$ are the identical transconductances and output resistances of NMOS transistors M1, M2; \$g_{m3}=g_{m4}=g_{pmos}, r_{O3}=r_{O4}=r_{pmos}\$ are the identical transconductances and output resistances of PMOS transistors M3, M4.
For the small signal analysis, you can substitute a resistor \$r_d = r_{O3}||(1/g_{m3})\$ for the diode connected M3, without changes in the eqs. 1-3:
but you cannot omit the contribution of \$r_{O3}\$, when doing calculations with finite output resistances of PMOS. If you're omitting \$1/r_{O3}\$, you should also omit \$1/r_{O4}\$, because technologically these transistors are usually made identical.
After doing not-excessively-cumbersome calculations you obtain
$$
V_{out} = {\frac {(2g_{pmos}r_{pmos}+1) g_m r_O r_{pmos}} {(g_{pmos}r_{pmos} + 1) (r_O + r_{pmos})}}V_{in}
$$
In the process you also obtain \$V_P\$:
$$
V_P = {\frac {(g_m r_O) (g_{pmos} r_{pmos})} {(g_m r_O + 1)(g_{pmos}r_{pmos}+1))}}{\frac {r_{pmos}} {(r_O + r_{pmos})}}V_{in}
$$
The first fraction in this expression is symmetric w.r.t. parameters of NMOS and PMOS transistors and asymptotically tends to unity as \$g_{pmos} r_{pmos}, \, g_m r_O\$ products grow, but the fraction \$ r_{pmos}/(r_O + r_{pmos})\$ favorizes \$r_O\$ over \$r_{pmos}\$ from the point of view of ability to zero \$V_P\$ with high output resistance. With finite \$r_O\$'s, \$V_P\$ never becomes "small signal ground", however great \$r_{pmos}\$ values you select.
But notice that, for \$V_P\$ to become "small signal ground", you should secure a finite output resistance of the PMOS transistors of the active load. The NMOS output resistance \$r_O\$ should become much greater then the PMOS output resistance \$r_{pmos}\$ of the load, \$r_O >> r_{pmos}\$, which agrees with the formulas, but inconsistent with the explanation given in the accepted answer. Another way to adjust the \$V_P\$ behavior is to consider the tail current's AC component, i.e., the finite output resistance of the \$I_{SS}\$ current source.
Removing both \$r_{O3}, \, r_{O4}\$ from the small signal model, you've got two ideal current sources connected in series, which is formally unacceptable. Notice that inserting the resistor R1 as in your fig. (b) does not help with current sources connected in series. The resistor R1 connected as in fig. (a) shunts M1, but not M2. High output resistance of active load transistors decreases the driving strength and increases the pair-matching sensitivity and stiffness of the diff pair, but also increases the voltage gain. High voltage gain is favorable for the opamp input stage.
The node P voltage becomes relatively input-insensitive with the sophisticated active load called the Lee load. This design has much better CMRR.
