# Low-side NMOS switch circuit

I built this circuit trying to learn how to drive a single HY3912W MOSFET. In the simulator, it acts as I expect.

I built it.

When I applied 6V to VAG and 5V for 1-second pulse to PWM every time the pulse is LOW VAJ draws about 3W power generating heat in the MOSFETs.

I UN-soldered the MOSFETs and put them in a cheep transistor tester that I do not really understand but I think it works.

The test results for 2N7000 Datasheet are as follows. They look fine to me.

The test results for BS250 are as follows. I do not really understand this tester but this doesn't look right to me. Why N-D-MOS (notice the D where the rest of the tests are an E) and why does line 3 read zero amperes yet on the other test it reads a capacitance and the diode is missing from the symbol on the screen? Is this defective?

I then tested a few more BS250 chips from the tray to find the rest have a capacitance and read N-E-MOS. I do not have any other PMOS chips for comparison.

I soldered new MOSFETS on the PCB and applied power. The same results, it just draws about 3W power when PWM is low so I think it has destroyed this PMOS as well.

What am I not understanding?

• I see various BS250 pinouts on the web...gate is always in the middle, with source/drain swapped on outside pins. Have you tried that PMOS "backwards"? Aug 16 at 12:01

I suspect you've got drain and source swapped, for Q1, the P-channel MOSFET.

When PWM-IN is low, the gates are both high (because of the inversion by Q6). If this circuit was working, then Q2 would be switched on, and Q1 off, but if Q1 had its drain and source swapped, its body diode would still be conducting, and getting hot.

Heating wouldn't occur when PWM-IN is high, because Q2 successfully switches off.

Don't handle MOSFET transistors without grounding yourself, they are very easy to damage with ESD.

If you don't trust the transistor tester to tell you the pinout of these MOSFETs, and you can't use a datasheet, use a multimeter in diode mode to locate the body diode. That will help you identify drain and source.

If you're still not sure, then build a safe circuit to test the device in isolation:

simulate this circuit – Schematic created using CircuitLab

$$\V_{OUT}\$$ should always be the logical inverse of $$\V_{IN}\$$. It will be immediately clear if you've swapped drain and source, because in one of the two states drain-source potential difference will be 0.6V or so.

# Extra

Since you are learning about this kind of thing, allow me to give you some extra pointers. I've taken the liberty of modelling this circuit's operation, in CircuitLab, to illustrate some issues with the design:

simulate this circuit

C1 is just to emulate the gate capacitance of the HY3912W that the circuit is suppose to drive. Here's a plot of The various voltages in the circuit, given a 5V square input, in blue here:

The brown trace is node G, the collector of Q6. As you can see, it falls fast, because Q6 switches on hard and very quickly, and is able to sink to ground a lot of current to discharge the gates of Q1 and Q2.

However, when Q6 switches off, its collector potential rises much more slowly, since the only source of current to re-charge those gates is R2. R2 can only pass a maximum of $$\\frac{6V}{10k\Omega}=600\mu A\$$. The two MOSFETs, Q1 and Q2, do a good job of converting that slow rise into a much sharper output transition at OUT (orange), which is why they are employed in this application.

A more troubling problem seems to be the delay between the falling input and the resulting rise of voltage at G (the interval between the two green markers). This is mainly due to the transistor taking ages to recover from deep saturation. This delay can be improved by driving the transistor Q6 into a shallower saturation, allowing it to evacuate its base region of charge more quickly.

The goal is to inject base current which is greater than that needed to saturate the transistor, but not too much. Given that this transistor has a current gain β of about 100, we should aim for a base current which is something like $$\\frac{1}{50}\$$ of collector current.

Another important consideration is that the higher Q6's base resistor R1, the slower Q6 will respond, due to parasitic capacitance present at the base, so we should also try to keep R1 as low as possible. So rather than increase R1, I would prefer to decrease collector resistance R2. Naturally this will increase current drawn from the power supply, but this is a balancing act.

Changing R1 from 10kΩ to 470Ω will increase the ratio of collector current to base current from about 1:1 to something like 50:1. That will increase collector current of course (to $$\\frac{6V}{470\Omega}=13mA\$$), but this has the added benefit of charging the gates of Q1 and Q2 much, much faster.

Here's the plot of voltages with R1 changed to 470Ω, in which you can see the delay greatly improved, as is the output fall time.

Lastly, there's shoot-through. That's when current flows directly from supply to ground via Q1 and Q2 while they are both partially conductive. If you could guarantee that Q1 and Q2 were never on at the same time, then shoot-through wouldn't happen, and designers go to great lengths to achieve that, with techniques such as dead-time. Here's a plot of current through Q1 and Q2 during transitions:

Current rises to over 200mA for brief periods, and you must ensure that this doesn't cause the power supply to droop momentarily during those transitions. Don't forget that other systems connected to the same supply can be affected too, not just your little section here.

The way to do that is with decoupling capacitors. A couple of ceramic capacitors, perhaps 1μF and 10nF in parallel, connected across the power supply, as close as possible to Q1 and Q2, should do the trick.

• thank you for this information, it is very helpful. i have found that my biggest problem is that i am unable to turn BS250 completely off by pulling base to ground. i have connected a 330 ohm resistor and LED to source and in order to turn the LED down dim enough not to be able to see any light BASE is pulled down to -4V. dose this make BS250 unsuitable for this switch. Aug 16 at 15:04
• It would help if you could measure Q6 collector voltage when PWN_IN is low, and tell me the result. Aug 16 at 15:50
• i do not currently have the circuit set up as i was trying to test just the PMOS transistor on a breadboard, trying to understand how to use them. this is the breadboard link. this is the current schematic link first LED to the left is 5V base, middle LED base is GND and right LED is -5V base. i just cannot understand why i cannot fully turn of the MOSFETs Aug 16 at 16:30
• 5V should hold the LED OFF and 0V should turn ON the LED ???? these chips marked BS250 cannot possibly be a PMOS, its driving me up the wall trying to work out if im just going mad, the LEDs are lighting the wrong way right??? Aug 16 at 16:49
• i have finally got to the bottom of my problem. amazingly i have a tray of components that are all marked BS250, about 20% of them are P-MOSFETS and 70% N-MOSFETS. im glad i had a cheepo transistor tester or i never would have worked that out, but i rely wish i hadent of have this tray of cheepo transistors, it has done my head in for hours. Aug 16 at 17:53

I have finally got to the bottom of my problem. amazingly i have a tray of components that are all marked BS250, about 20% of them are P-MOSFETS and 70% N-MOSFETS. im glad i had a cheepo transistor tester or I never would have worked that out, but i rely wish i hadent of have this tray of cheepo MOSFETs, it has done my head in for hours. even seeing it with my own eyes, I still struggle to believe that there are N-MOS and P-MOS transistors out there both marked with the same text stamped on the case.

• There are lots of recycled and fake components being sold, especially on eBay, but also probably on Banggood and AlieExpress. It's usually much better to order from reputable distributors like DigiKey and Mouser, often at similar prices. Aug 16 at 21:45
• clearly, I order most components from LCSC these days but this tray of MOSFETs has been in a rack in the stores for like 10 years or so, it could have come from anywhere. found about 50 P-MOSFETs in it and through the resit in the bin, i only needed 5 now anyway, i clearly need to order more PMOSFETs for next time, thanks for all the help:-) Aug 17 at 7:50

The heating is normal for that circuit, because it is not a very good circuit.

As there is nothing else than a 10k resistor to pull up the gate voltage, the voltage rises very slowly, and while the voltage is hafway going up, both transistors are halfway on, conducting current directly from supply to ground.

So the FETs must dissipate the power as heat. If it got damaged this may be the reason.

• i can understand heat during transition, but it is continuation drawing power whenever PWM is NOT 5V (the power from the 10k resistor R2 reaches the gates) so i feel like there is more to it than that. plus the output is NOT filly switching just fluctuating a bit. how do you suggest i improve the circuit? Aug 16 at 11:54

If I were making such a driver, I wouldn't necessarily use mosfets. And if I were using mosfets, I'd use parts with much lower maximum channel resistance.

In the circuits below, R10/L10 are a model of a GPIO pin driving the input, and R20/L20/C20 are the model of the HY3912W/A mosfet's gate.

It's enough to use two junction transistors. 2N3904/2N3906 work better than 2N2222/2N2907, since they have higher gain at the lower gate charging currents in this circuit (vs. the next one).

simulate this circuit – Schematic created using CircuitLab

The output rise- and fall-times are about 100ns:

The gate charge and discharge currents are fairly symmetric:

To speed up the gate voltage slew rate, an emitter-follower first stage can be added. The transistors have to be changed to 2N2222/2N2907, since higher currents are involved:

simulate this circuit

The gate rise- and fall-times are under 40ns.

The gate charge current peaks are about 5x higher than in the single-stage circuit, and require careful PCB layout and ample decoupling.