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In my project I have a 15 V power supply and I have to step it down to 3.3 V and 5 V for to use with PCB components. At first I tried using an LDO, but it heated up too much, to a point where it shutdown itself, so I had to change it to a buck converter.

Now I am worried about EMI and noise issues with this converter. I have directly followed design guides on the datasheet of buck converter (LM53600LQDSXTQ1).

My question is this layout good enough or should I make it 4 layers with separate grounds, or is there any other suggestions to implement?

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  • \$\begingroup\$ No separate grounds since you have no isolation. What’s your decoupling situation on input and output side? \$\endgroup\$
    – winny
    Aug 17 at 9:08
  • \$\begingroup\$ I have added the schematic. \$\endgroup\$ Aug 17 at 9:14
  • \$\begingroup\$ It's common design to use a buck regulator to take the voltage down to 5V and from there use a LDO to create a 3.3V RF supply. \$\endgroup\$
    – Lundin
    Aug 17 at 11:06
  • \$\begingroup\$ No ground plane? \$\endgroup\$
    – winny
    Aug 17 at 12:14
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    \$\begingroup\$ This is a board that would benefit a lot from being four-layer. It doesn't add that much cost (at least with the PCB fab I regularly use) to go from two to four layers, so I would recommend doing so if you were worried about price, at least see how much it would cost. Boards with more than four layers can get pricy, but four layers is, at least in my experience, not too bad. \$\endgroup\$
    – Hearth
    Aug 17 at 15:45

4 Answers 4

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Most radiated noise on PCBs is generated by current loops. Identify your current paths for every trace. The most common error I see even in professional PCBs is expecting a ground/power plane to provide a low inductance path back to the source where it is full of traces.

  1. Follow the reference layout in the data sheet to the letter. Pay strict attention to the SW node.

  2. Route traces on topside in one direction and bottom traces perpendicular. The QFP presents challenges in this regard, but spend extra effort to try and achieve. Even if a distance is very short, use vias to go around.

    Check out your 3.3 V trace. It almost completely encircles the QFP making it impossible to get the traces out of the micro.

  3. Route all power supply traces in a controlled fashion. Plan the return currents. Power supply return currents in the ground plane tend to follow the path directly beneath the outbound current trace unless the plane is broken by other traces. So visualize how the current flows in the ground plane to minimize the area of the current loop.

    The 16.8 Vin leaving J1-2 to J4 and J5 must return all the way back to J1-1.

    The 5V Vout leaving C21, C22 must return from all destinations back to the ground terminals of C21, C22.

    The 3.3 power supply has the same issues. The QFP of the micro makes this challenging so do your best.

  4. Use a ground plane at least on the bottom side and possibly on the topside as well. Do your best to route mostly on the topside. Plan for the bottom side traces to allow return currents in the plane to cleanly pass along the best path. Of course a 4-layer board will allow a pair of low inductance power/ground planes. The cost is coming down, but most circuits can be implemented with 2-layer boards.

  5. Place keep-outs in the ground plane under op-amp negative input node. Not just the pin but the whole node. Also keep-out under inductors.

  6. Keep the area of all current loops as small as possible. Be very picky about this. Re-plan your layout if necessary.

  7. Keep trace lengths as short as possible. Re-plan your layout if necessary.

  8. The AGND and DGND pins of various chips must be connected together at the chip. Many pros think these should be connected to separate ground planes. If there is any voltage drop between these pins there will be noise measured by the analog circuitry within the chip.

  9. Add more capacitance to long power lines.

  10. Decouple, decouple, decouple. Decoupling capacitors provide a low impedance local source of electrons for high speed transitions.

Be very strict and picky with your layout and routing. And did I mention to minimize the area of all current loops.

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    \$\begingroup\$ Well, it's a rule of thumb to always use 4 layers when dealing with QFP/QFN. And it's also a rule of thumb to always use 4 layers when designing switch regulators. And since we aren't living in the 1990s any longer, the cost difference between 2 and 4 layers is non-existent. So who can make a single, sound argument for using 2 layers here, I wonder... \$\endgroup\$
    – Lundin
    Aug 17 at 12:01
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    \$\begingroup\$ @Lundin Quote today from a board house: Qty.5, 100mmX100mm. 2-layer $5 for all five. 4-layer $25.97 for all 5. That is a 5 times difference. Definitely NOT non-existent price difference. Regardless, extra layers may not solve an RFI problem without proper layout and routing. \$\endgroup\$
    – RussellH
    Aug 17 at 18:05
  • \$\begingroup\$ Prices on low quantity prototypes might vary a lot, but I'd still say you are getting scammed. It might matter a lot if you created panels or if you are buying them one by one though. \$\endgroup\$
    – Lundin
    Aug 18 at 6:38
  • \$\begingroup\$ Thank you for the comments. I am studying the topics one-by-one. \$\endgroup\$ Aug 18 at 6:46
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I have directly followed design guides on the datasheet of buck converter

The data sheet gives these guidelines: -

enter image description here

Do you think having a two-layer board as you have show will meet those guidelines or do you have some mitigating circumstances that exempts you from the guidelines? In particular I'm referring to TI's mention of a ground plane. You should really try to follow those guidelines.

In addition TI mention this document: AN-1149 Layout Guidelines for Switching Power Supplies and it doesn't look like your design is based around this either.

Switching power supplies are pretty much always recommended as having a near-fill-ground plane and this is made a lot easier using a 4-layer board. Of course, as you develop analysis skills, you might be able to achieve good results with a two-layer board but this comes with risk (mitigated by experience and analysis).

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There is enough room for solder mask in between pads, but it's still recommended to not make a solid pour over the pads or have tracks directly going from one pad to the next.

Edit: Vcc is correct.

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  • \$\begingroup\$ It is also seems to be left floating on the datasheet suggested design schematic. But on the pin-out description, it says, it should be connected to the AGND on fixed versions. Which one i should do? Also connected pads are suggested in the datasheet recommended layout. \$\endgroup\$ Aug 18 at 6:43
  • \$\begingroup\$ Sorry, my bad, for LM53600LQDSXTQ1 it is correct. Datasheet indeed seems to also show a connection between the thermal pad and a corner pad. Not the the cleanest design for manufacturability. You probably won't see an error, but the problem is that there is more exposed copper for the pad. If it was between the pads there would be a risk of the solder in the pads to combine into a big blob that would lift the IC and cause it to not solder properly. \$\endgroup\$
    – Ralph
    Aug 18 at 18:15
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The entire layout is basically wishful thinking. There are all those very long power traces that will radiate like crazy, lots of thin stubs, etc. All those things taken together will make it barely functional.

At first I tried using an LDO, but it heated up too much

Most likely you didn't have good thermal heat sinking from the LDOs to the board. The LDO should be sitting on a large (say 0.5"x0.5" or bigger) copper polygon. That polygon should be stitched by thermal vias to another polygon on the bottom layer. It's ideal if the polygon can be GND, since then it's just stitched to the ground plane that's on the bottom of the board.

The entire bottom of the board should be a ground plane, with very slight interruptions. Try and get most of the signal routing done on the top, with only short trace segments on the bottom ("jumpers").

All of the GND polygons on the top layer have to be stitched with many small vias to the bottom layer. Especially around the switching regulator.

The thin traces to L1 are a no-no. Use polygons instead. Power input from the connector through decoupling caps and to U7 should be a polygon as well.

Relocate J3 etc. so that there's no long trace from the switcher output anymore.

Basically, make ground a plane, and keep all other power connections as short as possible, as fat as possible if there are appreciable currents flowing across them. Reorganize components on the board so that the power distribution is very compact, since you have to relegate almost the entire bottom side to a ground plane.

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