I've been reading through the 802.3 standards recently and am learning about alignment markers inserted as blocks in ethernet frames to deskew PCS channels.
While I can find information about the bit-by-bit content of these alignment markets, how would physical circuitry at the receiver use these bits to correct for skew? Is there some kind of digital feedback loop and delay circuitry involved as is seen in the clock recovery PLL?
In general, there is a CDR circuitry per the receiver at each lane. After the CDR the restored digital data (bits of per-lane bit stream) is buffered (FIFO'ed).
AMs are the digital contents (bit patterns) of the FEC frames, and intended to align the digital content received from the parallel lanes.
Therefore, although the phase shift between restored clocks at which the restored per-lane bits are written into the buffer may be a fractional multiple of the bit time, the phase shift with which a given per-lane bit stream is read from the buffer is always an integral multiple of the bit time. In other words, the read phase shifts are (integral) bit shifts.
So, AMs are in duty to find such the read bit shifts, no less but not more.
Legend: CDR = clock and data recovery; FEC = forward error correction; AM = alignment marker.
