# Can more fan-out be achieved with two inverters, and if so, how to choose which path?

This is a pretty theoretical question. My interest is digital circuits for CPU design.

Let's say I have some digital CMOS circuit composed of 50 transistors that implements some logical function. Let's say the practical fan-out limit of this circuit is 4, but I really need to connect it's output to 5 other gates.

Can I use a couple inverters on one of the output paths to "buffer" the signal and make it strong enough to drive the load? (That would be way better than duplicating a 50-transistor circuit.) And if so, how do I choose which path is the best choice for that double-inverter (or does it matter at all)?

• The double inverter will add delay (skew) relative to other which may or may not be a problem in your application. Maybe just the output section of your 50-transistor circuit can be duplicated, creating two identically-timed outputs. Aug 17 at 20:38
• @td127 Yes i thought of that too, but it seems simpler to just add a double inverter on one path because that's only 4 transistors with their own simple CMOS template. If i tried a custom alteration i would be paranoid about making sure its good CMOS. Aug 17 at 20:49

I'm assuming that your existing circuit cannot be modified, e.g. to use a higher-fanout pcell for its last gate or duplicate its output stage as td127's comment mentions.

Can I use a couple inverters on one of the output paths to "buffer" the signal and make it strong enough to drive the load?

Yes, buffering is an approach which is used in practice for high-fanout nets. I'm not sure off the top of my head whether this is just two inverters, or a more dedicated buffer pcell (my expertise is analog and my digital VLSI design knowledge is much more limited)

And if so, how do I choose which path is the best choice for that double-inverter

Propagation delay and timing analysis are relevant here. If you can buffer the path with more timing slack (on the setup path) you put the propagation delay of your buffer in a place where it affects your final performance less; likewise if skew is a concern the paths to buffer may be chosen so as to reduce the skew.

Sorry i don't really understand load and impedance at a fundamental level yet. Impedance is supposedly resistance combined with reactance, but these are DC circuits so that alone boggles my mind as to how reactance plays a role.

First, these aren't DC circuits. They have a DC component, but switching a signal between low and high is an AC phenomenon.

For CMOS, your load is quite reactive, since each gate input looks like a handful of capacitors. Here's a simple inverter with its major parasitic capacitances drawn in red:

These capacitances form the reactive load that we're concerned with when we talk about fanout - the gate-source capacitances show up as-is, while the gate-drain capacitances look even bigger than they are because they interact with the gain of the inverter. When you add up all of these effective capacitances (which are in parallel) across every load in the fanout, you end up with a total capacitance that the prior stage needs to drive; call it $$\C_L\$$.

We can roughly approximate the output transistors of the prior stage as a voltage source with an output impedance $$\R_o\$$, and we notice that the capacitors require a bit of time to charge, with the charging time proportional to $$\C_LR_o\$$. This is precisely why fanout is important: more $$\C_L\$$, more time needed for a given $$\R_o\$$. Too much time taken, and you're violating timing specs.

like if any one path is more "in need" of load help than the other.

If one path has a really long interconnect line, it could be worth buffering, since that interconnect line itself contributes parasitics including parasitic capacitance. I don't know what the relative contribution would be, since I haven't worked with long digital interconnects, and it depends on your silicon foundry process anyway.

• Propagation delay and timing analysis: I was assuming simple combinatorial logic for now, so was just gonna figure out the max delay of each circuit then add them up for the whole unit. I was more worried about load driving, like if any one path is more "in need" of load help than the other. Sorry i don't really understand load and impedance at a fundamental level yet. Impedance is supposedly resistance combined with reactance, but these are DC circuits so that alone boggles my mind as to how reactance plays a role. But i understand everything is analogue in practice. Aug 17 at 20:47
• @DrZ214 Oh, if you're looking for an analog treatment, I can certainly expand a bit when I'm free. In short. the thing is that these aren't DC circuits - they're changing state when the inputs change, and impedance (or capacitive load) are relevant and worth considering, even if you just handwave it as "inputs have capacitances, capacitances add in parallel". And as for combinational, if you want the thing to go as far as possible, put the delay on the part that's already faster, so you're not making the slowest path even slower. Aug 17 at 20:50
• Right they're changing state, but the current flow direction is always the same (or zero). So to me that ruled out AC. Maybe it was just wishful thinking because i find AC to be way more complicated, so i never looked deep into it. I have tried to look deeply into the magnetic side of electromagnetism but that is also very hard to understand. Aug 17 at 20:56
• @DrZ214 No, it's absolutely within the realm of AC, even if the "average" voltage is positive. When a signal goes high, it charges the capacitance between that signal and VSS and discharges the one between that signal and VDD. When it goes low, it discharges the capacitance between it and VSS, and charges the one between it and VDD. No need for electromagnetics; it can explained with circuit analysis alone. Once I'm home I'll try to add some diagrams. Aug 17 at 20:59
• @DrZ214 Some analog details added Aug 18 at 14:52