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Given a common PCB size of 100mm x 100mm, sub-RF frequencies (<20 kHz) and non-sensitive signals (as opposed to as measurement H-bridge) is there a real problem in routing traces of a symmetrical circuit (such as rectifier or motor driver output stage) on different layers or with different trace lengths?

I understand the importance of routing considerations at RF frequencies due to impedance and signal speed concerns, and with measurement circuits due to disturbance immunity concerns. But, what about other circuits like low frequency digital, analog or power? Have you encoutered any issues due to oddball routing in these cases?

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In a digital signal, or any kind of square wave, the fundamental frequency may be low but it is the rise time that determines the harmonic spread. For example, a microcontroller GPIO with a 2ns rise time, driving a LED in PWM at 1kHz through some long loose wires, will radiate trash all over the place in the hundreds of MHz.

Likewise, a PWM motor controller or a DC-DC converter may operate at a "low" frequency (few kHz or tens of kHz for the motor, few hundreds of kHz for the buck) but if it switches fast, the edges will be stiff... and it will radiate trash all over the place in the hundreds of MHz.

It is the rise time that matters. For example back in the day I had a crummy parallel port JTAG adapter. The signals sure could not be called "fast", it was damn slow. But the edges were fast, which means it had lots of high frequency content... and when going through wiring that is not a good transmission line, these high frequencies got screwed and phase shifted in many ways. The problem was the supplied ribbon cable, more precisely the connector pinout, which didn't have enough ground pins, plus a lack of termination resistors. So, the fast edges were distorted, there was ringing and crosstalk. And even if the signal itself was slow, the FPGA input receiving it was very fast, so when it saw a bit of ringing on the edge... it was more than fast enough to register two clock pulses where there was supposed to be only one. In a serial protocol, that's instant failure. And the JTAG didn't work.

Leaving aside emissions, the kind of very short noise spikes generated by fast switching and fast edges (even at a low repetition rate or frequency), or switching converters... can absolutely cause trouble, even on a digital signal. This can cause headaches, for example if the SPI clock gets registered as a double pulse only when the noise spike from another circuit happens exactly during the clock edge.

Another issue I had was a buck converter that would go into undervoltage protection unexpectedly. It turned out there was a few mm of trace causing common impedance coupling between the top MOSFET and the chip's VCC. So when the top MOSFET turned on, VCC dropped a bit (only during a few nanoseconds), and that was enough to trigger the UVLO comparator and reset the chip. The fix was to split the trace in two lengthwise with an x-acto. That's another case of low frequency, fast edges, thus high di/dt.

Answer to your comment about class AB amplifier:

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Current in both transistors in a halfwave rectified version of the output current. So if the traces are not routed close together, it will emit a corresponding magnetic field, which will couple into the input. This produces a small but measurable amount of distortion. Likewise letting the ground return of these distorted currents flow into a ground trace via wrong routing of ground to the supply caps creates a distorted voltage drop on the trace impedance, if the ground reference point of the amp is taken at the wrong place, you also get an increase in distortion. This one isn't about high speed, more about magnetic coupling and common impedance coupling, which work well at low frequency too.

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  • \$\begingroup\$ Thank you for intresting input on the high di/dt - case. Can you think of other situations when routing might be an issue? For example, let's take a analog sound amp as an example: do you believe that a 10kHz sound on a 50W speaker would be noticably affected if one trace ran far on layer 3 while other was short and on layer 1? Or in the case of a motor driver? \$\endgroup\$ Aug 18, 2022 at 11:39
  • \$\begingroup\$ It depends on loop area and path of return current. And how your pwm motor driver switches. \$\endgroup\$
    – bobflux
    Aug 18, 2022 at 12:12
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Proper HF routing recommendations should be always adopted if you need to pass EMI tests. Even low frequency electronics must do this, if it is to be used in a commercial product.

And then, you don't gain anything by delivering a subpar layout that might still work as opposed to a rugged layout that can deal with hardships.

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    \$\begingroup\$ If we always had the luxary of space and freedom I'd agree with your statement. ;) \$\endgroup\$ Aug 18, 2022 at 11:41
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    \$\begingroup\$ @NoobPointerException I don't think that EMI compliant design makes stuff larger in general. The thought process of untangling and minimizing current loops is similar to that of achieving a tight design. Think of SMPS. They are built as ultra-compact as possible because of EMI constraints. If you build large loops, your stuff will likely work but be less immune to noise and disturbances. \$\endgroup\$
    – tobalt
    Aug 18, 2022 at 11:59
  • \$\begingroup\$ Most EMI tests start at 150 kHz, so layout of truly low frequency circuits really does not matter. But like bobflux said, square waves have much higher harmonics than their fundamental frequency. And like you said, it still does matter for immunity. \$\endgroup\$
    – jpa
    Aug 18, 2022 at 17:27

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