Verilog netlist module instance starts with \

Question

I have a netlist exported from Innovus, and some module instance names start with \ .

DFRRQ_3VX1 \cnt_reg_reg[0]  (...)

In the testbench, I am forcing a module's input value, and it returns:

Hierarchical name lookup error

force DUT.cnt_reg_reg[0].D = 1'b1;

I saw a post about Verilog naming syntax, but I don't know how to implement it to do a hierarchical lookup.

Answer 1

This instance name is known as an escaped identifier. To avoid the error, you need to use the backslash and a space:

   force DUT.\cnt_reg_reg[0] .D = 1'b1;

Here is a complete code example:

module DUT;
    DFRRQ_3VX1 \cnt_reg_reg[0] ();
endmodule

module DFRRQ_3VX1 (input D);
    initial #1 $display("%m D=%b", D);
endmodule

module tb;
   initial begin
       force DUT.\cnt_reg_reg[0] .D = 1'b1;
       #5 $finish;
   end
endmodule

Refer to IEEE Std 1800-2017, section 12.4 Hierarchical names:

The period character shall be used to separate each of the names in the hierarchy, except for escaped identifiers embedded in the hierarchical name reference, which are followed by separators composed of white space and a period-character.

Also refer to section 2.7.1 Escaped identifiers:

Escaped identifiers shall start with the backslash character (\) and end with white space (space, tab, newline). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

The code runs on multiple simulators on EDAPlayground