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Suppose we have two signals: A and B. And we need to check that the rising edge of signal B is between 7.62ns and 7.77ns after the rising edge of signal A. In VHDL this can be done with two "wait-for-until" expressions.
SystemVerilog does not have direct translation of the compound VHDL wait statements. The simple forms can be translated
wait for delay → #delaywait on A → @Await until expression → wait (expression)If you needed to combine some of these forms together, they can be put into a fork/join_any block
VHDL:
wait until sig = 15 for 10 ns;
SV:
fork
wait(sig == 15);
#10ns;
join_any
SystemVerilog Assertions are not the best construct to catch timing errors, but they can be used
property p;
realtime timestamp;
@(posedge a) ('1, timestamp = $realtime) |=>
@(posedge b) $realtime - timestamp inside {[7.62ns:7.77ns]};
endproperty
fork/join_any block creates a process for each statement inside the block and waits for any one of the processes to complete before continuing after the block. In this case it is simply an OR of the conditions before continuing. Note that it does not terminate the remaining processes. There are other construct that can do that.
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