I have an example of I2C communication, but there is an error, and I can't figure it out.
The Start and Stop conditions are good, the address has 7 bits, data has 8 which is correct. I think the error is between ACK and D7, but not sure.
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1\$\begingroup\$ If it is it positive clock edge triggered it would produce an error according to your diagram. \$\endgroup\$– Andy akaAug 20, 2022 at 17:27
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\$\begingroup\$ Is the error in a real application or are you supposed to find the error in the bus sequence you posted (like for an assignment)? \$\endgroup\$– Sim SonAug 20, 2022 at 17:33
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\$\begingroup\$ this is an exercise, the error is intentionaly put. It is not a real application \$\endgroup\$– Christofor15Aug 20, 2022 at 17:47
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1\$\begingroup\$ For homework questions we expect you to demonstrate a substantial effort to find your own solution. What do you know about I2C and how the protocol is supposed to work? \$\endgroup\$– Elliot AldersonAug 20, 2022 at 18:32
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1\$\begingroup\$ You suspect the error to be between ACK and D7. But it looks fine to me (i.stack.imgur.com/rsoQF.png, UM10204). This "glitch" happens when the SDA line is handed back from the slave to the master. \$\endgroup\$– VelvelAug 20, 2022 at 19:53
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The master device should probably NACK after the data. Assuming this is the last transaction. No idea the context.
Edited: Corrected to say master instead of slave. Thanks @Seir for the correction.
