I am working on a circuit, part of which looks like this:circuit

Signal SW is switching the MOSFET on and off such that the nodes ac+ and ac- are shorted (modulated). When SW is high to turn on the MOSFET the waveform looks like this: turn_on_waveform

(MOSFET turns on at around 1.2020 ms), which is as expected. Signal V (ac+, ac-) is modulated from that particular moment.

The problem is when SW is going low to turn off the MOSFET. The waveform looks something like this:enter image description here

The MOSFET is turned off after 1.2060 ms. There is a dip (negative transient peak) in signal V(v_rect), which is lower than 0V when V(sw) goes low. Is this due to the gate-drain capacitance (Miller cap) and the SW signal being fed forward to node V_rect? This same transient peak can be seen during the turning ON of the switch.

  • \$\begingroup\$ Why is R2 in parallel with D1? \$\endgroup\$
    – Andy aka
    Aug 22, 2022 at 11:33
  • \$\begingroup\$ I am using the V(ac+) signal in another part of the circuit which requires R2 \$\endgroup\$
    – AlveyFrost
    Aug 22, 2022 at 11:37
  • \$\begingroup\$ Yes, I think this 30 ns glitch is from the Miller cap, since v_rect is a high impedance node. \$\endgroup\$
    – Jens
    Aug 22, 2022 at 13:36


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