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I'm using the MOSFET circuit presented below to switch the power supply in the PCB (low power). The problem is the current consumption during the ON state of P1, which is 0.5mA to keep-on the pmos (The current nmos drains is controlled by the resistor R). However, due to the noise levels, I'm not able to increase the value of that resistor in order to decrease the current drain (I tried experimentally other values such 15k, 20k, ...). I began to design a circuit to disconnect the pull-up using PNP when PMOS is turned on, but the circuit became complex and possibly more current consuming. Maybe there is a clever way to do it.

Resuming the circuit functioning: S1 and S2 signals can be used to drive the P1 PMOS. When S1 or S2 are high, the PMOS gate is set to 0V, and the PMOS turn on. When S1 and S2 are both low, 5V appears at the PMOS gate trough R pull-up.

OR circuit

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  • \$\begingroup\$ When S1 or S2 are both high <-- either? \$\endgroup\$
    – Andy aka
    Aug 24, 2022 at 9:53
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    \$\begingroup\$ Depending on how much gate charge P1 requires and how quickly you need to switch it between states, you could just use a 5 V CMOS OR gate instead of building the OR circuit from discretes. For example 74LVC1G32. \$\endgroup\$
    – The Photon
    Aug 24, 2022 at 14:07
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    \$\begingroup\$ You could add a capacitor (10 to 100 nF) parallel to R and increase R to 100 kohm or even more. This slows down the switching time of the P-FET but cancels the noise at the gate. \$\endgroup\$
    – Jens
    Aug 24, 2022 at 14:08
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    \$\begingroup\$ Something like a 74HC32 would take no more than 2uA if it wasn't driving an output. Much less than your 10k resistor. \$\endgroup\$
    – Finbarr
    Aug 24, 2022 at 15:26
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    \$\begingroup\$ @bmalbusca you could power it from the 5 V input, same as your circuit. And 74LVC1G32 takes only 10 uA in either 0 or 1 output state, so unless your application hardly ever delivers power to the load, it will be much more efficient than your existing solution. \$\endgroup\$
    – The Photon
    Aug 24, 2022 at 16:14

2 Answers 2

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You need the gate of P1 to be low, if either S1 or S2 are high. That's the behaviour of a NOR gate:

S1 S2 G
0 0 1
0 1 0
1 0 0
1 1 0

So, if you want no quiescent current to flow in any state, you could implement the classic static CMOS NOR gate:

schematic

simulate this circuit – Schematic created using CircuitLab

enter image description here

Current drawn by the gate:

enter image description here

P1 acts as an inverting stage, so \$V_{OUT}\$ becomes S1 OR S2. Also, ignore the voltage offsets, which are artificial to stack the graphs vertically; the actual signals are all 0V or 5V.

R1 is there to limit shoot-through current, but if your MOSFETs are small signal types, and you don't mind a few dozen milliamps flowing for a few nanoseconds at output transitions, you could omit R1. In any case, make sure you decouple the power supply adequately to provide those transient currents.

Alternatively, use a prepackaged NOR gate, like the 74HC1G02, 4001 or 74HC02:

schematic

simulate this circuit

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You could use any 5V CMOS buffer, say CD4050, 74HC08, etc.:

schematic

simulate this circuit – Schematic created using CircuitLab

The key idea is to filter 5V using a low-pass filter, with C1 directly across the supply pins of the buffer.

If your inputs are 3.3V level, and the buffer is a 74HCT type, then the mosfets are unnecessary:

schematic

simulate this circuit

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  • \$\begingroup\$ A question about the second schmatic: If only one input is active, the output shoot through current of 4 mA will drain C1 until fed by the input protection diode. The driving MCU output now feeds the output fight and I expect around 1.4 V at the combined outputs. This might indeed turn on M2, but is this the intended kind of operation? In this situation >200 uA passes R3. \$\endgroup\$
    – Jens
    Aug 26, 2022 at 13:53

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