# How do flash memories address the actual bit location?

I'm trying to understand flash memory, and while I can find lots of explanations for how individual cells are read/written to by directing some current across that cell, there is basically nothing explaining the circuit that directs current to that particular cell.

What I can find about multiplexers/memory decoders for RAM makes sense but I'm not sure it applies to flash. For example, I find it hard to believe that a 1 TB flash drive would have a multiplexing chip with 40 input wires and a trillion output wires (or even 2 such multiplexers, each with 20 input wires and a million output wires, if arranged in a grid like DRAM). If I were designing a flash memory multiplexer I would build some sort of tree of multiplexers, and to minimize power consumption I would try to arrange it so that they do not draw any power until they start to receive an input signal.

But, I can't find anything on how it actually works for flash. Can anyone point me to a reference or spec sheet?

• What's so unbelievable about two million wires? These are impressively dense structures, holding a LOT of data! They will be impressive no matter how you look at them :) Aug 26, 2022 at 16:05
• If a flash drive is 1TB that means it has 8 trillion wires in it somewhere - no getting around that! (Actually it could be perhaps QLC with 2 trillion wires, but not less than that) Aug 26, 2022 at 16:28
• You're right, there aren't 2 trillion wires. There are 2 trillion flash cell nodes, divided into a set of smaller blocks, each arranged in a grid array and accessed by row and column lines. The grid produces high-impedance outputs that are connected to shared wide read buses, avoiding muxes. But that's a high-level sketch view and there's plenty on this on the internet already written in detail. Aug 26, 2022 at 16:35
• @TonyM Multiplexing into that grid is still a monstrous addressing problem (1 million wires per side!). How are the smaller blocks addressed? How are the row and column lines addressed? Aug 26, 2022 at 17:04
• @TimWilliams Agree; my skepticism was about a single chip having 2-million outputs. As I said, a tree of chips such that the final layer has 2 million wires is reasonable to me. But is that how it actually works? Aug 26, 2022 at 17:06

I find it hard to believe that a 1 TB flash drive would have a multiplexing chip with 40 input wires and a trillion output wires

Scale down a bit.

Think about a chip with a 4096 bit locations and think about how these could be arranged to make addressing fairly easy. One idea that springs to mind is to arrange the bits as a cube of dimensions 16 x 16 x 16. So, three 4-bit identities can describe any one of the 4096 bit locations.

Image from here

And yes, scaling up takes some real engineering.

• I want to think about the 1 TB case, though! It seems to have qualitatively different aspects from scaled down versions. For example, memory at that scale isn't a cube, and maybe can't be because of heat dissipation (but if the multiplexers have negligible power consumption when idle, that might be wrong). Aug 26, 2022 at 17:04
• Okay, I can think of lots of virtual arrangements (with a d-ary tree being my preference). But is that how real flash devices work? Aug 26, 2022 at 17:11
• A cube is just a visual aid to see how things can be allocated virtually. 1 Tb of memory addressing could be broken down into 4 dimensions each with 10,000 individual locations for instance. Aug 26, 2022 at 17:13
• I looked through the linked paper and it discussed a lot of higher-level issues, but I didn't find anything about the specifics of how this works in real devices. For example, in the 3-d example you gave, since the third dimension is 4 bits/16 addresses, that means it needs 16 row decodes and 16 column decoders. With 4 dimensions of 10,000 locations each, that means there needs to be 100 million row decoders and column decoders. Is that what's actually etched into the chip? Aug 26, 2022 at 18:12
• I can't say precisely because it's probably IP. Aug 26, 2022 at 18:24

After more research, the other answer is completely right but I found this paper to provide some scale and context. I'll quote section 1.1 in its entirety (emphases mine):

The flash memory is spread across multiple flash chips, where each chip contains one or more flash dies, which are individual pieces of silicon wafer that are connected together to the pins of the chip. Contemporary SSDs typically have 4–16 chips per SSD, and can have as many as 16 dies per chip. Each chip is connected to one or more physical memory channels, and these memory channels are not shared across chips. A flash die operates independently of other flash dies, and contains between one and four planes. Each plane contains hundreds to thousands of flash blocks. Each block is a 2D array that contains hundreds of rows of flash cells (typically 256–1024 rows) where the rows store contiguous pieces of data. Much like banks in a multi-bank memory (e.g., DRAM banks [36, 130, 131, 143, 145, 147, 148, 188, 194, 195]), the planes can execute flash operations in parallel, but the planes within a die share a single set of data and control buses [...]. Hence, an operation can be started in a different plane in the same die in a pipelined manner, every cycle. Figure 2 shows how blocks are organized within chips across multiple channels. In the rest of this work, without loss of generality, we assume that a chip contains a single die.

Data in a block is written at the unit of a page, which is typically between 8 and 16 kB in size in NAND flash memory. All read and write operations are performed at the granularity of a page. Each block typically contains hundreds of pages. Blocks in each plane are numbered with an ID that is unique within the plane, but is shared across multiple planes. Within the block, each page is numbered in sequence. The controller firmware groups blocks with the same ID number across multiple chips and planes together into a superblock. Within each superblock, the pages with the same page number are considered a superpage. The controller opens one superblock (i.e., an empty superblock is selected for write operations) at a time, and typically writes data to the NAND flash memory one superpage at a time to improve sequential read/write performance and make error correction efficient, since some parity information is kept at superpage granularity (see Section 1.3.10). Having the ability to write to all of the pages in a superpage simultaneously, the SSD can fully exploit the internal parallelism offered by multiple planes/chips, which in turn maximizes write throughput.

This means, to get up to 1 TB, we get:

• a factor of 64,000 to 128,000 bits for free because that's the minimum granularity that the memory device actually wants to address (i.e., it doesn't even bother addressing into a page, it just returns the whole page)
• a factor of 100-1000 of pages/block (a straightforward amount for a multiplexer)
• a factor of 100-1000 of blocks/die (also straightforward for a multiplexer)
• a factor of 1-4 of dies/chip
• a factor of 1-16 of chips per actual SSD.

Multiply all those together and it can easily reach several terrabytes.

Then this thesis models the energy consumption by assuming non-addressed pages do not consume energy. So it seems reasonably safe to conclude that the page decoders have low-to-zero energy consumption unless they are themselves addressed by the block decoders.

It looks like chip and die addressing is a bit more high level, and the memory controller likely addresses all chips simultaneously for higher-throughput access, so there isn't a decoder/multiplexer at that level.

I'm still not entirely sure on whether the block/page decoders are split into row and column decoders, or whether blocks are columns and rows are pages. But that doesn't make a massive difference, given the other numbers.