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I was trying to use a microcontroller's 16-bit IO port to interface with a parallel display. I found that the IOs of a single port (let's say PORTB) are highly fragmented around the microcontroller:

STM32G pinout

For example in the image above, PB0~PB2 are located at the bottom right, PB3~PB9 are located at the top left, and PB10~PB15 are located at the bottom right.

Here is another example of a PIC32MM:

PIC32MM

This one is so chaotic you can't find 5 pins straight in a row!

And finally this one, Freescale Kinetis KL16:

Kinetis KL16 pinout

This one has a few sets of pins straight in a row, but the ports themselves are not complete; a bit of PTA, a few pins of PTB, and so on.

The questions:

  • I'm not familiar with the silicon underneath, but aren't the PORTS just a few MOSFETs and some other circuitry controlled from the signals (the bits) of a register? So physically, they should be in a row just like the register, or at least, not so chaotic that half the port is 1 cm away from the other half of it. Why are them designed like that?
  • I think some manufacturers prefer the pinout to be compatible with peripherals (e.g. SPI) and to be close to each other because no one needs 16 pins in a row these days. But many of these microcontrollers have some kind of remappable peripheral IO, and aside from that, what's the problem of having an SPI IO straight as the main PORT IO, so we could retain the 16-pin compatibility?
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    \$\begingroup\$ It's something that frustrates all of us, but unfortunately unless someone doing the actual chip design can weigh in here, we can only guess. It's certainly not required; there are some that have orderly pinouts e.g. AVR. (Though that's only 8 bits at a time, not 16 or 32.) \$\endgroup\$ Commented Aug 27, 2022 at 10:41
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    \$\begingroup\$ I've voted to reopen this question. It's quite reasonable, may give some insights to chip design, etc., and can be answered with facts and citations by someone involved in the design of such chips. \$\endgroup\$
    – Transistor
    Commented Aug 27, 2022 at 13:06
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    \$\begingroup\$ The question's been asked before, more or less: electronics.stackexchange.com/questions/437661/… electronics.stackexchange.com/questions/202168/… So far only one has an answer claiming design experience: electronics.stackexchange.com/questions/4394/… \$\endgroup\$ Commented Aug 27, 2022 at 14:57
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    \$\begingroup\$ I wouldn't call that highly fragmented ;) \$\endgroup\$
    – marcelm
    Commented Aug 29, 2022 at 14:18

4 Answers 4

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One of the reasons for distributing the individual IO pins associated with a bus around the periphery is to reduce problems that may arise from SSO (Simultaneous Switched Outputs).

When many outputs of a chip (MCU, FPGA, ASIC, etc) switch at the same time, the current spikes associated with that switching activity along with interconnect inductance on the chip can cause spikes in the GND rail, from dV=l(dI/dt), that can upset chip operation.

In order to ameliorate this problem, chip designers have implemented multiple IO power rails within the chip. There might be one power (and GND) rail for each side of the chip, or multiple rails depending on the size of the chip.

So by distributing the IO of a bus around the chip, the SSO noise is reduced because the transient current flows in separate paths in the various IO power and GND rails on the chip.

Note that besides distributing IO around a chip, SSO can also be helped by using slew rate control on the outputs, if that is a feature of the device you're using.

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  • \$\begingroup\$ So that's the reason that some MCUs, have a setting to allow GPIO output speed control like 2MHz, 10MHz ... ? \$\endgroup\$ Commented Aug 27, 2022 at 19:24
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    \$\begingroup\$ @TirdadSadriNejad it could be part of it, but I think that's more for EMI or signal integrity concerns. Slower switching = less power in the higher harmonics = less radiated energy and reflections in your traces. \$\endgroup\$
    – mbrig
    Commented Aug 28, 2022 at 6:43
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    \$\begingroup\$ It should be noted that the PIC32 part in the original question does in fact have a VDD/VSS pin pair on three sides of the chip (which supports what this answer says). \$\endgroup\$
    – user4574
    Commented Aug 28, 2022 at 15:04
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Once consideration not mentioned so far is compatibility with other devices in the manufacturer's portfolio.

There are too many possibilities to list, but some are:

  • The IC can be a drop-in replacement for another part (possibly for a particular use-case)
  • The same die may be used with another package and there compatibility requirements on the other package
  • The pins are dual/multi-function so the manufacturer wants (say) the SPI pins to be in the same place even though they are on port B on one chip but port C on another, again so that the IC is a simple replacement for another part.

Certainly during development we will be looking for risk-reduction when selecting an IC so if a manufacturer has a range of devices with nice compatible pinouts then that means that should something unexpected happen during development (e.g. we need more RAM, an extra serial port, the chip status goes from production to not recommended for new designs, we have difficulty getting hold of parts etc. etc.) then we might get away without having to re-layout the PCB or be able to do simple mods until the PCB can be revised.

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Modern day lower end MCUs rarely have an external 16 bit data/address bus. It makes no sense to constrain the pinout when there is no such requirement. Higher end parts have dedicated parallel interfaces, mainly for memories. These higher end parts will have the pinout optimized for such requirement.

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Here are a few reasons.

Many times these chips were designed as a custom for a specific customer who controlled the pinout. When you buy millions, pennies count. At a later date, if the customer agrees they can be sold on the merchant market, generally this is agreed upon before design starts.

Competitors will match pin-outs so they can fit an existing socket and gain some of that business.

Sometimes the semiconductor is second sourcing a custom part built by the customer. Wafers are expensive and any space savings is money in the pocket of the manufacturer.

Part of it is dictated by how the silicon is laid out, usually you do not want I/O adjacent to clock lines.

RF radiation is another consideration.

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