Help biasing this JFET buffer

I'm trying to make a simple JFET buffer but I am struggling to find clear instructions on how to calculate the bias resistors.

I've built a circuit which nearly works, but I'm getting well below unity gain. The resistor values are taken from a random design I found and I feel I'm not biasing the FET correctly.

I've got a nice 250 kHz sine wave going in at 4 Vpp but getting a 2 Vpp distorted one out.

• about biasing...with 8.2k source resistor, roughly 3V source-to-gate voltage is required to yield about .366mA FET current. That same 0.366mA flows through drain resistor, taking another 3V. So you've run out of voltage...VDD of 6V isn't enough here. Try it with higher VDD....you'll have some voltage headroom for drain voltage to swing without so much distortion. Aug 27, 2022 at 20:36
• thanks @glen_geek, that's useful info. for this project Vdd is fixed at 6V and the fet must be U310. Is it possible to improve the headroom by changing Rg & Rs ? I also think Rg is a bit low - might be better at 470k or 1M. Aug 27, 2022 at 20:50
• Yes try V+ = 16V for these R values, otherwise not much gain to be had except as a source follower at 6V. There is too much swing in Idss and Vt to get a stable operating point at low voltage for a common source. Aug 27, 2022 at 21:02
• An advantage of using a JFET amplifier is its very high input resistance. You need to keep RG high to keep the benefit of the JFET's high input resistance. RG defines the input resistance.
– user173271
Aug 27, 2022 at 21:10
• Where are your Design Specs? What can you possibly gain with 4Vpp input and some source impedance << Rg with a 6V supply. It makes no sense. Cg is not some series cap, but rather the shunt gate input capacitance. Once you choose desired transfer function and I/O impedance and voltage range, SNR etc. then you can choose a design but this design has many issues especially without specs. Aug 28, 2022 at 3:03

Here are a couple of JFET amplifiers which I designed some time ago.

Here is a circuit with the typical model biased with ~2V at the source and ~4V at the drain.

Gain is ~3.5.

For a power supply voltage in this range, something like a BF862 would be better. Here is a gain of 100:

Equal drain and source resistors mean that if the transistor is saturated, then the minimum voltage on the drain is 3V. In cutoff, the maximum drain voltage is 6V. So $$\V_{Omax} = 3V_{pp}\$$. If the biasing was such that the entire supply voltage could be used the out put would be limited to 6Vpp. As @glen_geek commented, increasing the supply voltage will increase the available amplitude.

The spec sheet indicates that the minimum $$\V_{GSoff}\$$ is -2.5V. Take some measurements to determine where your gate-source voltage is. It must be between 0V and -2.5V. Probably -1.0V would be appropriate. Decrease the source resistance until you get that. Then decrease the drain resistance if possible until you get the Vpp you desire.

EDIT: The 3.3pF capacitor on the input and output are way too small. It needs to be at least 100 times larger. The the gate source capacitance will knock the signal way down.

The gate bias resistor should be in the megaohms.

Random values don't work. Find some good JFET textbooks,

• thanks @RussellH - that's useful information. i'm stuck with 6V here, just struggling to find a decent worked example online. sadly, these days many blogs are just incomplete copies of each other :-( Aug 27, 2022 at 21:31