Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
I'm trying to make a simple JFET buffer but I am struggling to find clear instructions on how to calculate the bias resistors.
I've built a circuit which nearly works, but I'm getting well below unity gain. The resistor values are taken from a random design I found and I feel I'm not biasing the FET correctly.
I've got a nice 250 kHz sine wave going in at 4 Vpp but getting a 2 Vpp distorted one out.
Here are a couple of JFET amplifiers which I designed some time ago.
Here is a circuit with the typical model biased with ~2V at the source and ~4V at the drain.
Gain is ~3.5.
For a power supply voltage in this range, something like a BF862 would be better. Here is a gain of 100:
Equal drain and source resistors mean that if the transistor is saturated, then the minimum voltage on the drain is 3V. In cutoff, the maximum drain voltage is 6V. So \$V_{Omax} = 3V_{pp}\$. If the biasing was such that the entire supply voltage could be used the out put would be limited to 6Vpp. As @glen_geek commented, increasing the supply voltage will increase the available amplitude.
The spec sheet indicates that the minimum \$V_{GSoff}\$ is -2.5V. Take some measurements to determine where your gate-source voltage is. It must be between 0V and -2.5V. Probably -1.0V would be appropriate. Decrease the source resistance until you get that. Then decrease the drain resistance if possible until you get the Vpp you desire.
EDIT: The 3.3pF capacitor on the input and output are way too small. It needs to be at least 100 times larger. The the gate source capacitance will knock the signal way down.
The gate bias resistor should be in the megaohms.
Random values don't work. Find some good JFET textbooks,
