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I am designing a small four layer PCB with KiCad. The purpose of this PCB is to control and monitor the lights of a car (not for road use) and without having to resort to old relays and fuses.

I have opted for high Infineon switches as they have all the safety features I need. Everything is controlled by a WROOM ESP32 S3 via MQTT. As the power IC of the ESP I used a MAX16904 with 3.3 and 600 mA output.

My question is related to power/ground planes.

Since I have four PCB layers, I thought of creating three power supply planes (12V) top, in1 and in2 all crossed by vias (via stitching) in order to reduce the current and the heat produced. The last layer (bottom) creates a gnd plane. Under the IC power supply I made a ground plane that crosses all 4 levels thanks to the vias.

Photos of the PCB (I don't have the contour lines yet because I still lack a couple of components related to the logic part.) I also tried to divide the circuit into two parts: the upper part is related to power while the lower part on the logic. I hope I was clear enough.

I leave you the screenshots below.

PCB

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  • \$\begingroup\$ Is it possible, to make things clear, to make images of each separate layer? \$\endgroup\$
    – RemyHx
    Aug 28, 2022 at 15:28
  • \$\begingroup\$ Assuming that the same current goes through both GND and 12V traces for each circuit, using three layers for 12V and only one for GND does not look very useful. I would rather order the layers as follows: signal, signal ground, power, power ground. \$\endgroup\$
    – Maple
    Aug 28, 2022 at 16:56

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I’m sure others will cover the functional issues, but from manufacturability perspective alone: unequal thermal masses on the pads of 2-terminal devices increase the chance of tombstoning. I imagine this might be a problem for the diodes, and will be an absolute killer for the small 0603/0805 devices. Ensure that all the 2-terminal devices have comparable thermal impedance to the board substrate on both ends. The layout as shown has thermal impedance differences of well over an order of magnitude – that’s a big problem.

When connecting to multiple pins on the ICs, don’t use a thick trace. It’s hard to get right, and the rounded cap on the trace gets in the way. Instead, use copper fill polygons to make such connections, and connect the trace to those polygons.

In this particular circuit, I’d route most if not all high current traces using polygons. You’re paying for all that copper either way, may as well use it :) (in this particular case since the circuits are not sensitive to the small distributed capacitance).

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  • \$\begingroup\$ Yep, those small parts sitting with one side on heavy traces is the first thing that catches an eye. I would not go as far as replacing traces with polygons though. Making polygon pads around chip pins or customizing chip footprint with such pads will have the same effect but more routing flexibility. \$\endgroup\$
    – Maple
    Aug 28, 2022 at 16:48
  • \$\begingroup\$ @Maple Ok Thanks for the reply. I will use for the outputs of the polygons (in fact I had not thought about it). What do you mean by functional problems? Also I have a question about how to improve the thermal part for 0805 components. What should I do? \$\endgroup\$
    – Nik_01
    Aug 30, 2022 at 18:57
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enter image description hereI improved my pcb in this way:

  • Using polygons for output this way I have more surface
  • Divisions of the 4 layers in this way: 1layer signal + ground plane, 2 ground plane layer, 3 power plane layer while the 4 signal + 3.3v plane.
  • To improve the thermal part of the ic I put a couple of ways through the board
  • In order to distribute the current in the best possible way, I made some routes that connect to the power level.
  • Also on the input of the 12v I made a layer on the F MASK level so I have the copper uncovered and it is better. Other things to improve I do not see them. I leave you a couple of screenshots below. Thank you all
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