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The below image is from ST micro document. The document says
"A negative injection current on any analog pin (or a closely positioned digital input pin) may introduce leakage current into the ADC input. The worst case is the adjacent analog channel. A negative injection current is introduced when VAIN < VSS, causing current to flow out from the I/O pin."
I understood how injection current is generated. But may I know how this injection current causes a leakage current in the adjacent channel.
But may I know how this injection current causes a leakage current in the adjacent channel.
This is a CMOS process, so bringing inputs below the substrate potential (GND) will slightly forward bias the body diodes of nearby MOS devices. This will be a local effect, since the substrate has finite conductance, and thus the currents are kept localized to the area nearest to the I/O structures for the aggressor pin. There may also be other isolation structures that confine such leakage currents only to a few adjacent pins. Obviously this depends on what process the MCU was made on, and how fancy was its layout.
Since the analog pin I/O structures are likely adjacent on the die (chip), the biggest effect is on the neighboring analog pins. Once the substrate starts conducting, the I/Os in the conductive area are all leaking current to the substrate.
ST does not say how it can happen. If the effect was layout dependant it would not appear in the documentation unless it was in an app note. If it is internal, they are just letting us know so that they are off the hook for warranty. How you deal with it is up to you. For example, don't let \$V_{AIN}<0\$ occur if it will interfere with performance..
