I have this circuit where the voltage \$V_A = -4.6V\$ is imposed.

I made the hypothesis that the transistor is saturated. Then I calculated \$i_B\$ through KVL:

$$-2 + R_Ci_E + V_{EBon} + R_Bi_B + V_A = 0 \iff i_B = \frac{-V_A -0.6 + 2}{R_B} = 6x10^{-6} A$$.

If it is saturated, then I should have \$V_{BC} > 0\$ and \$V_{BE} > 0\$. In this case \$V_A + i_BR_B = -4.6 - 1.487 = -6.087 V\$. And \$V_{BE} = 2-(-6.087) > 0\$, but is not 0.6V. So it should be working in active mode? Also, if it is in saturation mode, what would the current through \$i_C\$ be? Would it be safe to say that, in saturation mode, \$i_C = i_E + i_B\$?

I sorry if the question is unreasonable, but I'm struggling to understand the relations and conditions for saturation mode (I think I grasped a bit for active mode).

enter image description here

  • \$\begingroup\$ Where does the -5 come from? \$\endgroup\$
    – Andy aka
    Sep 1, 2022 at 11:28
  • \$\begingroup\$ @Andyaka it was a typo! It was -2V \$\endgroup\$
    – ludicrous
    Sep 1, 2022 at 11:47
  • \$\begingroup\$ Check the numbers in your first equation. \$\endgroup\$ Sep 1, 2022 at 11:59

2 Answers 2


The KVL says \$+2\:\text{V} - \mid v_{_\text{BE}}\mid - \mid i_{_\text{B}}\mid\cdot R_{_\text{B}}=V_{_\text{A}}\$ or: \$\mid\:\, i_{_\text{B}}\mid\,=\frac{+2\:\text{V}- V_{_\text{A}} - \mid v_{_\text{BE}}\mid}{R_{_\text{B}}}=600\:\mu\text{A}\$. The way I read your text, it doesn't look like you got that figure. The numerator should work out to \$6\:\text{V}\$ and the denomnator is obviously \$10\:\text{k}\Omega\$. That fraction produces \$600\:\mu\text{A}\$, not \$6\:\mu\text{A}\$.

With that in hand, you can estimate that the collector current (if the BJT has \$\beta=20\$ when it is in active mode) may be as high as about \$12\:\text{mA}\$. That, together with the collector load of \$1\:\text{k}\Omega\$, yields a predicted voltage drop across the collector load of \$12\:\text{V}\$. But you know that's not possible, as this would mean that the collector would be sitting at \$+12\:\text{V}\$ with respect to ground. And you don't have access to a power supply rail that high.

So, in this case, the collector load will push the collector pin as close as possible towards the emitter voltage and thereby saturate the BJT. Given your data, the collector pin should go to within \$200\:\text{mV}\$ of \$+2\:\text{V}\$; at \$+1.8\:\text{V}\$. So this means the collector current magnitude is more likely going to be \$1.8\:\text{mA}\$ and not the \$12\:\text{mA}\$ earlier predicted assuming active mode operation.

In reality? The collector might be even closer to the emitter, so the collector current magnitude might be a smidge higher than that. But not much more.


I don't understand your KVL equation. There's a term \$R_CI_E\$ which shouldn't appear in there, because it does not form part of the loop this equation is dealing with. Then, even though that term magically disappears in your rearrangement, everything's correct but you still get the wrong answer for \$I_B\$. You somehow got 6μA, when it should be 600μA.

Here's your circuit, annotated to help my explanation:


simulate this circuit – Schematic created using CircuitLab

Considering the loop consisting of nodes E, B and D, \$R_C\$ isn't part of it, and won't appear in any KVL equation we derive for that loop. There are a few ways to go about applying KVL here, but I'll start at node A, and go downwards and clockwise.

First we encounter a potential decrease \$V_{EB}\$ across the base emitter junction, which would make the KVL term negative. Then we have a further decrease of whatever voltage appears across \$R_B\$ (another negative term), and finally an increase in potential from -4.6V to 2V:

$$ \begin{aligned} -V_{BE} - R_BI_B + \left[(+2)-(-4.6)\right] &= 0 \\ \\ -0.6 - R_BI_B + 6.6 &= 0 \\ \\ R_BI_B &= 6.6 - 0.6 \\ \\ &= 6.0 \\ \\ I_B &= \frac{6.0}{R_B} \\ \\ &= \frac{6.0}{10k} \\ \\ &= 600\mu A \\ \\ \end{aligned} $$

All this assumes that the base-emitter junction is forward biased, which it is, and is not blocking current.

There are limits to the amount of collector current \$I_C\$ we can expect to see. If the transistor is off, obviously there's no collector current. It's not off, because \$I_B \ne 0\$. When the transistor is saturated, \$V_{CE} = 0.2V\$, and we can apply KVL again (to the loop consisting of nodes E, C and G) to find saturation current \$I_{CSAT}\$:

$$ \begin{aligned} -0.2 - I_{CSAT}R_C + 2.0 &= 0 \\ \\ I_{CSAT} &= \frac{2.0 - 0.2}{R_C} \\ \\ &= \frac{1.8}{1k} \\ \\ &= 1.8mA \end{aligned} $$

Collector current cannot exceed 1.8mA. If, when we use the transistor's current gain to calculate \$I_C\$, we obtain more than 1.8mA, the transistor is saturated:

$$ \begin{aligned} I_C &= \beta I_B \\ \\ &= 20 \times 600\mu A \\ \\ &= 12mA \end{aligned} $$

That's not possible, this transistor is saturated, and:

$$ I_C = 1.8mA $$


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