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I'm trying to convert a 3V3 UART to 1V8 UART with an open drain buffer, but the output of the buffer is always high.

See the schematic below for the circuit. On the input to the buffer, there is a 0V - 3V3 UART, working exactly as it should. On the output, I'd expect a 0v to 1V8 UART. But I'm getting a 1V8 always high.

It's not a dead chip, as the same problem persists over multiple PCBs (10) - there are no shorts, the resistance values are correct and the supply rails are stable. For testing the output of the buffer is not connected to the downstream device.

What is going on?

Schematic of buffer in question

The markings on the chip:

The markings on the open-drain buffer

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    \$\begingroup\$ What markings are on the chip? \$\endgroup\$ Sep 1, 2022 at 22:30
  • \$\begingroup\$ Is it possible that the chip is mounted 180-degrees off? Which package are you using? \$\endgroup\$ Sep 1, 2022 at 23:41
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    \$\begingroup\$ Using DRY package - chip marking is "HL" - as far as I can tell (it is tiny), the chip is correctly mounted \$\endgroup\$ Sep 1, 2022 at 23:45
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    \$\begingroup\$ Is it possible that you got counterfeit chips? Desolder one of them, put them on a breadboard adapter, and just test them to see if they work at all. \$\endgroup\$ Sep 2, 2022 at 1:18
  • \$\begingroup\$ The board seems awfully sparse of GND plane stitch holes. That pour on the top layer is largely useless by itself. There should be a via right next to each GND terminal - both chip pins and capacitor pads. Take a differential wideband probe and measure voltage between C304.GND and U301.GND. It may be that there's lots of offset/noise. \$\endgroup\$ Sep 2, 2022 at 1:20

1 Answer 1

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All you need is a divider, no logic needed:

schematic

simulate this circuit – Schematic created using CircuitLab

Assuming C_LOAD=50pF load capacitance due to trace parasitic capacitance, and input capacitance of the MCU, the circuit mostly retains the rise- and fall-times of the source signal. Realistically, the 1.8V output will swing 10%-90% in less than 50ns. C1 can be tweaked and likely lowered to limit overshoot. In many circuits, C_LOAD will be effectively lower, and thus C1 will be proportionally lower as well.

L1 models C1's series inductance.

On the pre-production board, C_LOAD should be measured at 100kHz or 1MHz, with R1 and R2 removed, and then C1 chosen to equal about 6/5*C_LOAD.

As shown the input and output signal waveforms are:

3.3V and 1.8V UART waveforms

If you also need step-up conversion from 1.8V to 3.3V, that can be done too without ICs - in that case, you'd need to clarify in the question.

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  • \$\begingroup\$ Yeah, this works when there is a known and controlled source impedance - but the devices that plug into the input of this buffer are varied. In other places on the PCB, I use dividers where there is controlled impedance - in this case, I can't - hence the buffer. \$\endgroup\$ Sep 2, 2022 at 2:47
  • \$\begingroup\$ @skipper_the_penguin Makes sense. At a cost of an extra resistor and a capacitor, one can just go with dividers everywhere and use a push-pull buffer (non open-drain). \$\endgroup\$ Sep 2, 2022 at 12:32

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