RC circuit with equivalent up and down delay times

I have a basic RC delay circuit which has an R value of 1M ohm and C value of 4uF. Normally the voltage input is not connected, but when it connects it will be 3.3V voltage. A gpio is reading the voltage output of the RC circuit this is the only connection of the output of this circuit.

My question is what will happen when I fully charge the capacitor and then disconnect my input? Will the capacitor's transition to GND be much longer than it took to transition from GND to 3.3V?

Do I need to add a resistor on the output side of the circuit to make sure my rise and fall delays are equivalent?

Without a resistor on the output, the capacitor will charge to 99.3% of full charge in 5 RC time constants (20 seconds). If the input is disconnected, the capacitor will remain charged although leakage current will slowly drain the charge. If the input is switched to zero volts (GND), the capacitor will discharge at the same rate as it charged.

If you add a resistor, such as another 1 Mohm, it will charge to half the applied voltage (because of the voltage divider), but the time constant will be according to the parallel resistance of the two resistors. When input is removed, it will discharge to zero according to the time constant determined by the resistor in parallel with the capacitor.

Here's a simulation showing the two conditions.

With nothing connected to either input or output (which is the case you describe, assuming input is "high impedance" and output is also a very high input impedance ADC or something similar), there's no path via which the capacitor can charge or discharge. It will simply retain its existing charge state and voltage.

When the input is enabled, at 3.3V, then the capacitor charges via R613, with a time constant of $$\R_{613}C_{613}\$$. When the input returns to a high impedance state, the capacitor just sits there, unchanging, except for a slow discharge due to leakage current.

Adding a resistor, as you suggested, would alter the resistance of the charge and discharge paths, and solve nothing. You still have a different path impedance in each state, and you still have asymmetric behaviour.

If the input source actually returned to 0V, instead of becoming high a impedance, then the charge and discharge path impedance would not change between states, and you would have the symmetry you desire. To achieve this behaviour you could insert a stage to translate the two conditions of "high impedance" or "3.3V" into low impedance "0V" or "3.3V" sources:

simulate this circuit – Schematic created using CircuitLab

The buffer stage (which could be any non-inverting digital gate, such as AND, also shown) does not have a high impedance output state, and will always provide a solid, low impedance source of 0V or 3.3V, to obtain charge/discharge symmetry.

The buffer's input still requires an explicit low/high potential, and so it has a weak pull down resistor to ensure that a high-impedance state of IN will result in 0V there.