[Design of Analog CMOS Integrated Circuits by Razavi]
Can someone explain to me why in Fig 3.71, if M1 and M2 have the same dimensions, that it is equivalent to a single transistor with 2L and same W? I don't understand.
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Below is the layout of a single nmos transistor it consists of a polysilicon gate with a piece of n type material on either side. It has a width W and length L. These terms are often confused, L refers to the length of the channel from one side to the other and W is the width of the channel from the top to the bottom of the device as drawn.
Now lets wire two of these in series. The interconnect is represented by simple lines in reality it typically involves metal layers and vias.
We can move these together and combine the n regions in the middle into one region. This is very commonly done in silicon design.
As the gates are common we can go ahead and move the two gate regions together forming a single transistor of length 2l and width w.
As a first order approximation comparing the properties of transistors in one technology, the properties of the transistor are dependant only on W L and the voltage gradient across the gate. Looking at the steps above these are maintained throughout the merger process.
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\$\begingroup\$ Fantastic answer and step by step illustration!! \$\endgroup\$ Commented Sep 3, 2022 at 18:57
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1\$\begingroup\$ The question refers to the “poor man’s cascode” where the top transistor would have a lower threshold voltage to keep the bottom transistor saturated—not sure you can combine them in that case. Also, considering second order effects and identical transistors, I think a single long fet would have less overlap capacitance and junction leakage. \$\endgroup\$– DavidG25Commented Sep 9, 2022 at 15:39