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[Design of Analog CMOS Integrated Circuits by Razavi]

The author introduces a differential pair with source degenration which helps 'soften' the Vin/Vout characteristics of a differential pair: enter image description here

He then says that this has a major drawback that the source degeneration resistors consume extra voltage headroom which reduce the minimum swing we can achieve on output nodes X and Y. To solve this, he suggests the following circuit

enter image description here

I am having some difficulty understanding Fig 4.28 and how it is operating exactly. Could someone please provide some more insight into this?

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I am having some difficulty understanding Fig 4.28

That must mean you are happy with figure 4.27 so, I'll begin there: -

enter image description here

Because current source \$I_{SS}\$ has infinite impedance (as all current sources have), it makes no difference if it is split into two halves and connected to each source as per figure 4.28.

This simplification does slightly alter the DC conditions due to 4.28 not having a DC volt drop across \$R_{S1}\$ and \$R_{S2}\$ but this can be ignored if you want to analyse the AC conditions.

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    \$\begingroup\$ But in this case, how are we still getting the benefit of the source degeneration (i.e. softening the curve)? Is it when there is a CM voltage bias imbalance between gate of M1 and M2? \$\endgroup\$ Sep 5, 2022 at 20:03
  • \$\begingroup\$ The current source has infinite impedance so it can be ignored hence, source degeneration is exactly the same as it is in figure 4.27 \$\endgroup\$
    – Andy aka
    Sep 5, 2022 at 20:20
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Is it when there is a CM voltage bias imbalance between gate of M1 and M2?

Almost.
It is a reduction in the common mode source bias to the negative rail with 1/2 current mirrors only.

Rs adds to the RdsOn of each M1,M2 and thus reduces the gain. But when split Rs is used between the source and Norton sink it increases DC offset to the Vss rail.

Using a current mirror directly to the sources does not change the differential Gate voltage or differential source voltage, nor the AC gain with Rs+Rs=2Rs. Only the Common mode Vs has reduced.

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