# 555 TIMER ic: TI Datasheet: not able to understand these lines

I have studying the 555 timer IC by experimenting and working out the internals. I now have a good understanding, and hence visited the application note in the datasheet, only to find this statement.

The words: "sequence", "timing delay", "storage time" ; confuses me. There has been no reference/definition of these words before its usage here.

What I understood from my experimenting and knowledge of 555 timer IC, comparators and RC circuits is that:

• In monostable mode, initially, the trigger pin is kept >1/3Vcc.
• We do a momentary pull down (is that called triggering the circuit?), making the trigger go to (<1/3Vcc) voltage level
• the corresponding comparator (Say COMP1), outputs HIGH.
• Discharge transistor is still ON, so threshold is still GNDed
• Now input to SR FF is S=1, R=0 => Qbar = 0 => turning off the discharge transistor and driving output pin HIGH
• Note that the Trigger pin is high, meaning COMP1 output is low
• so S=0, R=0 => output is previous state! - so output pin still stays HIGH
• Meanwhile, The capacitor connected to threshold pin charges and reaches 2/3Vcc after some time
• once this voltage is reached, the corresponding comparator (COMP2), outputs HIGH, thus the input to SR FF is S=0, R=1 => Qbar=1 =>turning ON the discharge transistor and driving the output pin low.

-I understand that trigger pin can be kept LOW for longer durations of time too, but eventually threshold pin starts to work, and that's an entirely a separate session of discussion - but I do understand what happens in that case.

ACTUAL QUESTION:

1. is the word "sequence" referring to time when output pin is in HIGH voltage level or is the sequence of TRIGGER voltage level being high, momentarily going low and then going high?

2. "timing interval" - is it referred to the time, the trigger pin is LOW (that momentary time?)

3. "storage time" - I understand that comparators are not storing anything, but what do they mean by this? Do they mean, the comparator will take 10us to follow any input change?

• Yes, "comparator storage" time is misleadingly bad English, and unforgivable in using to write a technical spec. Commented Sep 6, 2022 at 11:51

2. Timing interval refers to the output pulse width $$\\approx1.1 R_A\cdot C\$$. It is unrelated to the input trigger pulse width, provided the input pulse width is short enough.