Standard cell design flow in an ASIC design flow

Question

I have a question regarding the standard cell design flow in an ASIC design flow.

That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured design flow directly follows, which basically means that the lithographic layers include specialized design blocks like memories, controllers, PLLs and others. In some sense they are also tidily coupled with an FPGA since FPGAs also often incorporate some predefined blocks like memories, PLLs and so on.

On the other side of the spectrum there is the full custom design flow where the designer needs to specify the placing of every single transistor of the device. This means that all lithographic layers need to be customized for a full custom design.

Somewhere in between there is the standard cell design flow. I do understand that a standard cell basically encapsulates the functionality of a specific gate or cell. We can have cells that implement an AND gate, an OR gate, or even something like a full adder, PLL, or a flip-flop.

But even with a standard cell design flow the foundry would still need to create all the lithographic layers for the design. Otherwise it wouldn't really differ from a gate array design flow. If the foundries actually need to manufacture every layer where does the benefit of a standard cell design stand beside the obvious simpler design flow and lesser risks in the implementation?

Is the standard cell design flow basically a full custom design flow but with predefined cells? If not what are the differences? I could imagine that the manufacturing process of the lithographic layers for a standard cell design could be easier for the foundry since their production pipelines already are configured for their standard cells. However I fail to find any information that would confirm my speculations.

What I try to understand is how a standard cell design flow differs from a full custom one from the manufacturing perspective. I would also appreciate any sources that would clarify this topic.

Answer 1

A gate array can use wafers with transistors pre-diffused into the substrate. The logic then uses customer-defined metal layers to connect them as needed. This approach reduces masking costs and other NREs, but will not have the best performance or density (and thus, cost.) They're suitable for simpler, digital chips as being somewhat cheaper than an FPGA if the volumes justify it.

Gate arrays do tend to lock you into that one vendor, another disadvantage in managing cost and supply.

At the other extreme, full custom chips start with blank silicon. Transistors and interconnect are placed as needed for the design (today, with some automation, but still with a lot of designer input.)

In the past, all chips were designed this way, transistor-by-transistor, before standard cells became the norm. These days you'll see this done mainly with mixed-signal or high-performance blocks, which need tight control over their physical design to achieve their target specifications (think blocks like PLLs, DACs, ADCs, serdes PHYs and so forth.)

Compared to gate arrays, full custom chips require all mask layers, from diffusion on up, but can be very compact. However, the risk of design spin is higher than with gate array - either through design bugs or because the chip failed to to meet all of its process/voltage/temperature (PVT) conditions.

Full custom chips target a specific process. This also locks you in to that vendor.

Standard cell methodology splits the difference between gate array and full custom by offering a pre-qualified logic and I/O library characterized for a specific process over its PVT range, and uses row/column placement of cells in a grid to aid power distribution. It has its origins with Mead and Conway, as laid out in their paper and later this book.

Standard cell methodology makes design synthesis more regular and predictable, because the cells have vendor-guaranteed performance. Thus, design risk is lower and designer productivity much higher. It also makes supporting multiple process vendors more realistic, something that's next to impossible with full custom, and to a lesser extent, gate array. This helps manage cost and supply.

It's also possible to migrate standard cell to smaller geometry with less effort than is required for full custom. This is a huge benefit to design and reuse, as an ASIC architecture moves through its lifecycle to improve cost, power consumption and performance.

Like full custom, standard-cell flows require full mask sets, and they can be very expensive. However, with standard cell design success is likely much higher, so the mask risk is lower.

Industry experience has shown that the benefits achieved with standard cell flow - productivity, design portability, and risk reduction - makes it the go-to methodology for the overwhelming majority of ASICs today.

Still, there's a place for custom layout. Modern ASICs will use a combination of standard cell for random logic, pre-qualified full-custom blocks for specialty mixed-signal and high-performance I/O, and hand-optimized blocks for performance-critical and area-intensive elements with regular structures such as ALUs and RAMs. The custom and hand-optimized blocks will placed as macros within a standard-cell design framework.