I am designing pcb for AT86RF215M tranceiver. The datasheet for it states that:

AVSS is the analog ground; DVSS is the digital ground voltage. The analog and the digital grounds should be separated on the PCB and only connected at a single point on the PCB.

So I guess that digital and analog ground should be connected at one point near the power supply. The problem is that evaluation board ATREB215-XPRO does not follow that rule. It is 4 layer PCB.


The analog and digital pins are connected to via. Ad via is connected to both ground layers. Both two GROUNDS.

I don't know what approach is better? I can't figure out.

  • 5
    \$\begingroup\$ There's a lot of debate about this topic. But since you've got an evaluation board design that works, you should copy that design -- including the layer stackup and the components placement. As long as the high-current ground return loops have minimal area, and the power return loop currents don't flow through sensitive areas, using a single groundplane is generally fine. \$\endgroup\$
    – MarkU
    Sep 7, 2022 at 19:13
  • \$\begingroup\$ If in doubt, follow the eval board. \$\endgroup\$ Sep 7, 2022 at 22:59
  • \$\begingroup\$ It's not uncommon for an IC to have separate analog and digital grounds pins, which are connected in the evaluation board. For example, the MAX31856MUD+ thermocouple IC has separate ground pins, but the MAX31856EVSYS evaluation board has only one ground. As others have said, if the evaluation board works with one ground, do that. \$\endgroup\$
    – C. Dunn
    Sep 9, 2022 at 14:59

2 Answers 2


This is common problem that is misunderstood. The pin labels indicate which "ground" domain is used internally in the chip. In the chip it is difficult to connect these domains with a low inductive connection so they are brought externally to be connected.

Why the datasheet insists not to connect these pins together is a mystery. A reference lay out should be provided if it is important.

If there is any transient voltage between these pins it will interfere with performances. Separate paths to a common point at the power supply adds inductance in both the digital and analog grounds.

Split ground planes are becoming rarer. It is better to use a clean solid ground plane. However, You must layout the components so that the currents in the plane follow a path that minimizes the loop inductance in the path. This can be challenging for 2 layer boards. Even vias through internal layers on 4-layer boards can deflect the current path causing inductance.

The contradiction that you noticed is interesting. What would I do? I would connect the pins directly together on a ground plane, unless there is a valid electronic reason (which has not been given) to do otherwise.


Thanks for help.

I will follow the reference design. If the receiver sensitivity and EM radiation will be in range than everything is ok. If not I will rethink the PCB design.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.