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I am designing a PCB that needs two adjacent Ethernet ports, both at 1Gbps speed.

The first Ethernet port (J5) is broken out directly from the processor module (Raspberry Pi Compute Module 4).

The second Ethernet port (J6) is provided by an Intel WG82579 PCIe to Ethernet bridge. The PCIe bus is also sourced by the CM4.

I calculated my trace and space for 100 ohm impedance matching and laid out my design to minimize vias, length match the differential pairs, and provide spacing between pairs to avoid crosstalk. My layout can be seen in the image below:

enter image description here

I'm quite happy that I have been able to keep almost 100% of the high speed differential routing on the top layer (red) of the PCB. My goal is to keep the bottom layer as low-noise as possible so I can put analog audio circuitry there.

However, as I have been reviewing my work, I have several concerns:

  1. Copper under magnetics. I have seen multiple application notes recommending that no copper, traces or GND planes, should extend beneath the Ethernet magnetics. I am currently violating that rule in order to route the Ethernet without using vias. Would it be better to use vias and remove the traces beneath the Ethernet magnetics? (T1 and T2 in image) To do this, I'd need to add vias to basically all of my Ethernet traces.
  2. Grounding. I based my GND scheme on what I found in the Raspberry Pi CM4 IO Board reference design. The reference design does not have a separate GND plane for the isolated side of the Ethernet port, and it allows the GND plane to extend beneath the Ethernet port. However, their design uses an RJ45 connector with integrated magnetics. My design uses separate components for the magnetics and the RJ45. Should I implement separate chassis GND planes for each Ethernet connector? Or, just leave the area under the Ethernet connectors as a copper-free area?

Relevant schematic sections: enter image description here enter image description here

RPi CM4 IO Board reference schematic section: Full schematic link here enter image description here

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  • \$\begingroup\$ This sounds like it is made against suggestions. Check appnotes that describe how to work with discrete magnetics. This circuit does not look like it survives passive PoE. Also what are the components under the connector? Show the schematics. \$\endgroup\$
    – Justme
    Sep 9, 2022 at 14:22
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    \$\begingroup\$ Have you considered using magjacks, which have the standard ethernet magnetics built in? That might afford you easier routing. \$\endgroup\$
    – Hearth
    Sep 9, 2022 at 14:59
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    \$\begingroup\$ I’ll add that your Bob Smith termination is wrong. Should have a separate 75 ohm to each center tap, terminated to a 2kV cap. More here: electronics.stackexchange.com/questions/229312/… \$\endgroup\$ Sep 9, 2022 at 20:45
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    \$\begingroup\$ Also, you’ll generally get better results with loosely coupled differential pairs. Tightly coupled pairs like you have are more sensitive to PCB fabrication variations. You’ll see different line width etching in horizontal vs diagonal vs vertical lines. Tightly coupled pairs have much more impedance variation, setting up reflections. There is no benefit to tightly coupled lines, contrary to what so many app notes claim, except in very dense PCBs which just have no space for routing. You really want to think about this as two single ended lines that carry signals. \$\endgroup\$
    – 65Roadster
    Apr 1, 2023 at 5:01
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    \$\begingroup\$ To expand on @65Roadster, if you abandon the zeal to have tightly coupled pairs, you also get more space for return current vias. So vias aren't such a huge problem. Place 1-4 return current vias right beside the signal via, going from the upper reference plane to the lower reference plane. Impedance will be a little disturbed, but it is not a desaster, you can put a few of them, but maybe not 10+. \$\endgroup\$
    – tobalt
    Apr 1, 2023 at 5:22

2 Answers 2

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As stated in comments by hacktastical:

I’ll add that your Bob Smith termination is wrong. Should have a separate 75 ohm to each center tap, terminated to a 2kV cap. More here: Is my Bob Smith termination valid for Ethernet 100 Mb/s?

Also, I would do straight routing on the IC side so that you can clear away GND under the magnetics, and do the swizzling on the cable side. Once you fix the Bob Smith of course.

As stated in comments by 65Roadster:

If you look at your skew budget I think you’ll see that you don’t need the bump outs to make the lines precisely the same drawn length. I’d guess you have > 0.25” of mismatch skew budget at 1Gbps. So you can just route the lines cleanly. The bumps cause impedance discontinuities which can show up in the eye. The ground return reference can be quite important, however.

Also, you’ll generally get better results with loosely coupled differential pairs. Tightly coupled pairs like you have are more sensitive to PCB fabrication variations. You’ll see different line width etching in horizontal vs diagonal vs vertical lines. Tightly coupled pairs have much more impedance variation, setting up reflections. There is no benefit to tightly coupled lines, contrary to what so many app notes claim, except in very dense PCBs which just have no space for routing. You really want to think about this as two single ended lines that carry signals.

As stated in a comment by tobalt:

To expand on [65Roadster's above comment], if you abandon the zeal to have tightly coupled pairs, you also get more space for return current vias. So vias aren't such a huge problem. Place 1-4 return current vias right beside the signal via, going from the upper reference plane to the lower reference plane. Impedance will be a little disturbed, but it is not a disaster. You can put a few of them, but maybe not 10+. [Copy edited]

Tim Williams adds:

See: How do you align parallel connectors (e.g. Raspberry Pi CM4) in production?
It seems fully breaking out the board is not recommended, even though the accompanying IO board does it, among others; you may get lucky, but you may also find intermittent or unreliable connections as the connectors are stressed and have very little motion themselves (they're very tight connectors). They're also likely to move between versions (as warned in the datasheet).

Regarding traces under magnetics, it can be a poor idea because there are intense and complex stray fields under the transformers, which can couple back into the traces underneath and degrade signal quality. (This is true even though Ethernet magnetics typically use toroidal transformers; it is less true of toroids in general, compared to other transformer styles -- but not absent, and we're probably talking small distances here, like 1mm away from a 6mm toroid.) I'm sure it would still work; the actual amount of coupling might be some percent. Still, that's coupling that can be avoided.

Solid ground plane underneath is probably fine. Note that isolation is required, and it's the perfect place to introduce that separation, so it's usually cleared of copper on all layers.

Regarding one of 65Roadster's above quoted comments: I would merely temper it by noting that Ethernet is a quite slow interface, as high-speed interfaces go -- with a 125MHz symbol rate, it is quite tolerant of layout and impedance errors. The PCIe lanes will be more critical; but again, PCIe is designed with usability in mind, and is quite tolerant of poor quality media, e.g. lossy FR-4. Not to say you can't, or shouldn't, be mindful of good layout, or to attempt an optimal solution -- just that you're mainly tweaking maximum cable length limits, and EMI performance (which can have subtle and hard-to-define impacts on operation).

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Copper under magnetics. I have seen multiple application notes recommending that no copper, traces or GND planes, should extend beneath the Ethernet magnetics. I am currently violating that rule in order to route the Ethernet without using vias. Would it be better to use vias and remove the traces beneath the Ethernet magnetics? (T1 and T2 in image) To do this, I'd need to add vias to basically all of my Ethernet traces.

I would think vias would be a worse way to route due to the extra inductance added (really have to check this with an signal integrity tool). There will be a slight amount of capacitance between the wires in the magnetics and the traces. I would think this would amount to less than 0.5pf and would probably be about as much as the crosstalk between diff pairs.

Grounding. I based my GND scheme on what I found in the Raspberry Pi CM4 IO Board reference design. The reference design does not have a separate GND plane for the isolated side of the Ethernet port, and it allows the GND plane to extend beneath the Ethernet port. However, their design uses an RJ45 connector with integrated magnetics. My design uses separate components for the magnetics and the RJ45. Should I implement separate chassis GND planes for each Ethernet connector?

It really depends on if you need isolation or not. If the ground planes are connected, the design will not be isolated from ESD. The real thing is to think about the return currents from ESD that is coming through the cable. In most ESD events the ground will be the pathway. With an isolated design, you could connect chassis ground to the isolated section on the magnetics and diodes and the ESD return pathway would be through the chassis ground (which in many products is connected to earth ground through the power supply).

The other option is to connect both grounds together with the ESD return current going out through the power supply ground.

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  • \$\begingroup\$ Thank you for the reply. I am planning on having isolated Ethernet ports. I am updating my schematic to move the ESD protection to the PHY side of the transformer, and changing the Ethernet connector shell pins to their own Chassis GND (with the Bob Smith circuit terminating to the Ethernet chassis GND) \$\endgroup\$ Sep 12, 2022 at 15:56
  • \$\begingroup\$ meta.stackexchange.com/questions/126180/… \$\endgroup\$
    – Voltage Spike
    Sep 12, 2022 at 15:58

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